Live Webinar: Analyzing DDRx: Guarantee Your Margins Before You Build and Ship Boards

Live Webinar: Analyzing DDRx: Guarantee Your Margins Before You Build and Ship Boards

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Overview
DDRx memory interfaces are ubiquitous in today’s designs, yet validating them is surprisingly complex, requiring thousands of simulations and waveform measurements. In fact, the latest data rates are well into the bandwidth range usually associated only with SERDES channels; many designers consider high-end DDRx design to be more difficult than low-end SERDES signaling. Are routing complexities forcing you to deviate from recommended vendor guidelines? Would you like to know what your real DDRx design margins are, and have a chance to improve them before you release your next board? This session will explain the use of HyperLynx’s DDRx Wizard, and preview its upcoming support for the new DDR4 standard.

 

What You Will Learn

  • Advances in DDRx interfaces, and their impact on design
  • Designing and validating DDRx interfaces
  • Defining constraints for the PCB design process

 

Who Should Attend

  • Signal integrity specialists
  • Design engineers
  • Engineering managers
  • Project managers

 

Details

What: Analyzing DDR2/3/4 Memory Interfaces: Guarantee Your Margins Before You Build and Ship Boards

When: Thursday 23rd of January 2014

Where: Online

Time: 15:00 PM CET

Duration: 1 hour

Registration: Web