If only I had known! I would have ....

Design errors, included?

If only I had known! I would have …….

 

Does it sound familiar to hear your engineer or yourself say after the error was discovered: ”If only I had known! I would have …“

 

But let’s be honest, could he/she or you have known? And did either of you had the time to review thoroughly? So don’t be afraid to ask the main question:

“Can somebody or something help me analyzing to find the design errors?”

 

If you don’t dare to ask yourself that question, don’t spent any more time on this article. But if you dare and would like to have some help, then continue reading this article.

 

Mentor Graphics delivers an Application called HyperLynx DRC that can analyze the design data in such a way that is similar to your interpretation of the design. HyperLynx DRC works with objects and knows its characteristics in order to conduct the analysis.
For example:

 

A piece of copper forms a conductor, antenna or something else. And two pieces of copper have a relation, not only in distance but also in coupling. In reality this means that they have a function, and, depending on how you look at them, this function can be good or bad. So a piece of copper connected to a pin, becomes a net and transports electrical signals with their good & bad characteristics. (It conducts but it radiates as well.)

 

Drawing information can be a board outline or a contour, or other intelligent information.

 

Components can be classified using their characteristics. Also there is a possibility to reuse external available information, like IBIS models. 

 

Now store all this information into different object classes and you will have an easy to query intelligent database. That’s where the power of HyperLynx DRC lies. You can easily access the information and manipulate it by:

 

logical operations such as  AND, OR, XOR, …

changing  it with grow, shrink, …

investigating  it with measure, find and compare

using the included field solver information to discover items like coupling information.

 

It all depends, of course, on what you’re looking for. On top of this, the outcome of this manipulation can be displayed as: fail, path or something in-between, and you can even add you’re prior experiences as advice.

 

All to help you find “The Error included” in your design. Now you know where to look and so you can take preventative actions.

Wow, that was a mouth full. So if you bear with me a little bit longer, I will try to illustrate it with some examples.

 

Example A: Electrical (Vertical Reference Plane Change)

 

Purpose:

Check if signal traces have a solid reference beneath them. Signals require an adjacent solid reference plane to allow for continuous return current path, so reducing the risk of common-mode radiation.

 

This is how your list of problems is reported.

 

Clicking on one of the actions will give the following options to review them.

 

Mark it

Show the hole net involved

Where on the board

 

Causing the return current to flow somewhere, resulting in common mode interference to other signals.  If you only would have ”added a via”, the problem would have been eliminated .

 

Example B: Mechanical (Filter Placement)

 

Purpose:

Check if connectors have filters placed close to the connector pins to be effective at suppressing radiation emissions.

 

This is how your list of problems is displayed.

 

Clicking of one of the actions will give the following options to review them.

 

Mark it

Show the hole net involved

 

If you only would have ”added a filter”. The questions remain: should I add a filter to prevent any problems, or can I ignore it because this is a well shielded net on the outside? Whatever the best solution is, now I can make a wise decision or consult my review partners.

 

Example C: Combined (IO Coupling)

 

 

Purpose:

Check for excessive Coupling of high-speed traces to I/O nets which creates a risk of High-Frequency noise leaving the system through the I/O Net.

 

Once again this is how your list of problems are reported.

 

Followed by the options to review them.

Mark it

Select I/O Victim

Select HS Agressor

 

Causing the nets to couple into an I/O_net signals. If you only would have ”Moved the signals a bit further apart”, the problem would have been eliminated.

 

Conclusion

It is interesting to see how you can prevent “The Hidden / included design error” leaving the design intact “if you only would have known”.  And there are 23 standard rules included in the HyperLynx DRC application. And of course, very important, you can add (unlimited) your own rules.

 

The next questions you could ask:

- Where does the information come from?

- What extra data does HyperLynx DRC need, in order to interpret my data correctly?

- What is the extra workload?

 

Let’s answer these questions in the next Newsletter.  Find the hidden / included design error. I will explain then in detail the effort that is needed to run a design against existing rules. And how you can add your own rules in HyperLynx DRC.

 

And if you’re too curious and cannot wait until the next Newsletter, please contact us via info@innofour.com or give us a call. We’re at your service.

 

Laury Watervoort

Senior Application Engineer at InnoFour