Tanner Analog IC Design

Tanner Analog IC Design Flow

Complete, integrated analog design flow that is flexible and easy to use, speeding your time to working silicon

The Tanner Analog IC design environment (formerly HiPer Silicon Analog design flow) increases productivity from design, simulation, implementation, physical layout and verification, to foundry-proven tape-out.

 

  • OpenAccess and iPDK support
  • Accurate SPICE simulator compatible with HSPICE and Verilog-A
  • View simulation results directly on the schematic
  • Complete hierarchical layout editor with SDL and manual-assisted routing
  • Real-time, interactive DRC
  • Automatically generates current mirrors, differential pairs, and arrays
  • Calibre®-compatible, hierarchical DRC and netlist extraction 
  • Extract RC parasitics with fast 2D or ultra-accurate 3D

 

Design and Simulation

Tanner S-Edit Schematic Capture

User friendly schematic capture environment for even the most complex analog/mixed-signal designs. Learn More ►

 

Tanner T-Spice Simulation

Fast, accurate, foundry-proven simulation for demanding analog/mixed-signal designs. Learn More ►

 

Tanner Waveform Viewer

Intuitive interface for viewing, comparing and analyzing simulation results. Learn More ►

 

Layout

Tanner L-Edit IC Layout

A complete analog/mixed-signal IC physical design environment that is flexible and highly configurable. Learn More ►

 

Verification

Tanner Verify DRC and LVS

Comprehensive AMS IC design-rule checking (DRC) and netlist extraction that's fast and easy to use. Learn More ►

 

Tanner Parasitic Extraction

Fast, accurate extraction of circuit parasitics to model device behavior and verify design performance. Learn More ►

 

 T-Spice Simulation Datasheet ►