ModelSim/Questa 10.5 beta

ModelSim/Questa 10.5 beta

As a valued ModelSim/Questa customer, we invite you to participate in the ModelSim 10.5 beta program. The purpose of the beta program is to give you an opportunity to provide direct feedback to our development team on our new features, ultimately resulting in a high quality release. You will receive a 90 day license for your testing purposes and instructions on how to access the software and support once you complete the beta form.  The beta will start on Sept 15 and complete on Nov 15.



ModelSim PE/DE 10.5 Beta Highlights:

  • Support for Windows 8.1 and improved license response on Windows
  • Improved debug support for VHDL dynamic Access Types
  • Improved VHDL and mixed VHDL/Verilog performance
  • Improved SystemVerilog messages and Virtual Interfaces
  • New fine grained code coverage control to improve performance
  • (with SystemC option) New support for SystemC 2.3.1 and SCV (beta2)


For the highlights below, VM(Verification Manager) is included with both Questa Prime and Ultra, PA(PowerAware), IF(inFact intelligent Test Bench) and VIS(Visualizer Debug) are included with Questa Ultra only, and Multi-Core(MC2 Option) is an option for both products and included with this beta.


Questa 10.5 Beta Highlights:

  • Improved SystemVerilog performance
  • Improved VHDL and mixed VHDL/Verilog performance
  • Improved performance for VHDL FPGA libraries
  • Added QFD(Questa Fast Dumping) support for VHDL and VCD dumping
  • New support for SystemC 2.3.1 and SCV
  • New SystemVerilog nettype support for real number modeling
  • Allowing real constraints for solver
  • Fine grained Code Coverage control for improved performance
  • Improved testplan tracking with new operators in rule expressions and rule aliases (VM)
  • New TestPlan Author(VM)
  • Run Manager (VRM) ease of use and HTML reporting performance improvements. (VM)
  • Simulation Distribution Manager support for session checkpoint and restore (IF)
  • Support for modeling constructs, including fixed-size arrays of structs and wide integers (IF)
  • Support for graph runtime progress logging(IF)
  • Xprop for VHDL – pass mode only (xprop)
  • New PA  Liberty Debug Window(PA)
  • Improved PA Checks and Standalone and Interactive checking capability(without needing to run simulation)(PA)
  • Improve PA simulation performance (PA)
  • Improved PA Coverage modeling (PA)
  • Questa Ultra now contains licenses for the Visualizer Debug Environment(VIS)
    • High performance/capacity debug specializing in post-sim debug
    • Easy, intuitive use model and powerful RTL connectivity debug
    • Full Featured UVM/SV debug in post-sim mode
    • Smaller files and faster dumping to QWAV format with Questa QFD
    • New Interactive and macro debug with 10.5


We look forward to your input and feedback and appreciate your effort towards improving our ModelSim release.


21st August 2017 BOM Connector 7.6 Released
20th July 2017 Release of FloTHERM v12
29th August 2016 PADS VX.2 Now Available
29th February 2016 Sherlock User Forum
1st February 2016 TLA Winner 2015
25th September 2015 ModelSim/Questa 10.5 beta
4th August 2015 New PADS Solutions!
29th June 2015 UVM Framework
23rd June 2015 PCB Sketch Router
21st April 2015 HDL Designer 2015.1 Release
19th February 2015 BOM Connector™
14th December 2014 Multi-board PCB Systems Design
9th September 2014 New course: Introduction to UVM
20th May 2014 Mentor PCB Forum
18th March 2014 Xpedition VX release
3rd February 2014 DfR Solutions - Best of 2013
22nd October 2012 Dongle discontinuations
19th October 2012 PADS 9.5 Now Available!
20th April 2011 Introducing Questa Core
1st February 2011 PADS 9.3 available
22nd November 2010 Why customers choose BluePrint
30th June 2010 PADS9.2 Available
8th June 2010 5 Reasons to Adopt PLM
18th March 2010 Mentor-Valor Acquisition
15th February 2010 InnoFour goes Scandinavia
18th January 2010 PADS v9.1 available
9th October 2009 CAM350 v10.1 available
26th May 2009 Introducing PADS v9.0
2nd February 2009 CAM350-150 Bundle Introduction