Accelerating FPGA VHDL Verification

Dates

This course is not yet planned.

Accelerating FPGA VHDL Verification

FPGA-development is one of the most interesting fields in advanced product development, and the possibilities in modern FPGAs are enormous, but so is also the complexity.

 

Description

On average half the development time for an FPGA is spent on verification.
It is possible to significantly reduce this time, and major reductions can be accomplished with just minor adjustments. It is all about Overview, Readability, Maintainability and Reuse at all levels – and you achieve all of this with the right methodology and a good structured architecture.

 

This is a 3-day course in FPGA-verification – on how to reduce development time and at the same time improve the quality. This is also a unique opportunity to learn the newly open sourced Universal VHDL Verification Methodology (UVVM).

You will learn

This course focuses on FPGA- verification and how you can build your testbenches in a structured way. Theory is mixed with practical examples and hands on tutorials. The course will also cover general important verification issues like coverage, BFMs, debugging, randomisation, etc.

After the course you will know how to structure an FPGA-verification platform and how to implement your testbenches and write test sequencer – so that even SW and HW developers can understand them. You will also have the complete UVVM, VHDL-based verification platform with you and the knowledge on how to use it in your organization.

Presenter is Espen Tallaksen, from BITVIS – FPGA-expert and the architect of UVVM.

 

Covered Topics

Issues

  • Verification time - Schedule / Man-hour savings of 20-80% is possible
  • Overview, Structure, Readability, Maintainability, Reuse
  • Test bench architecture - Most testbenches are insufficiently structured. A good architecture results in all the benefits above
  • DUT corner cases - Difficult to reach, which often results in FPGA bugs. Risk could be reduced to a minimum

 

Agenda

  • Making a simple VHDL test bench step-by-step
  • Using VHDL constructs like records, globals, procedures to make a better testbench
  • Applying logs, alerts, checkers and BFMs.
  • Making an advanced VHDL test bench step-by-step
  • Assertions, coverage, debuggers, monitors
  • Controlling Constrained Random and Functional Coverage within UVVM
  • Verification components and testbench architecture for advanced Verification
  • Verification reuse and preparations for reuse
  • Making testbenches as simple as possible – adapting to the DUT complexity
  • Examples and labs using UVVM (Universal VHDL Verification Methodology) – from simple testbenches to advanced verification components

 

Prerequisites

  • Working knowledge of VHDL and ModelSim or Riviera Pro
  • Some experience with test benches and verification using VHDL simulators

 

Practical and pragmatic approaches to Faster, Cheaper and Safer FPGA-Development.