Bitvis

 

 

VISITING ADDRESS:
Strøket 3

1383 Asker, Norway

www.bitvis.no

 

CONTACT INFORMATION

Espen Tallaksen, CEO
Phone: +47 934 21 277
espen.tallaksen@bitvis.no

 

William Braathen
Sales and marketing
Phone: +47 906 45 766
william.braathen@bitvis.no

 

General enquiries
Phone: +47 66 98 87 59
info@bitvis.no

 

Markets & Applications:

Data communication, Telecom, Healthcare, Industrial, Oil&Gas, Defence, Avionics, Space.

 

Services:

FPGA development, Embedded software development, FPGA courses, Verification Methodology and Libraries

 

Region:

Europe, Nordic countries

 

Bitvis AS is a privately held design centre that helps customers develop FPGA, Embedded Software and SoC-FPGAs. With any part of the development, but also with methodology, reviews – and as a sparring partner.

We invest significantly in methodology improvement – including tools and libraries – primarily to improve quality. We focus on Overview, Readability, Maintainability and Extensibility for the same reason. A side effect of this is more efficient development, simpler and safer reuse, and a far more customer oriented handover.

 

Bitvis is the maintainer of Universal VHDL Verification Methodology (UVVM) – the new open source VHDL testbench methodology and library that allows complex verification scenarios to be handled in a simple way, - so that anyone can make advanced testbenches with a structured architecture, and control the Device Under Test (DUT) with simple and very understandable commands. The library allows a testbench kick-start due to the already available Verification Components and BFMs for AXI4-lite/stream, Avalon MM, UART, I2C, etc. UVVM may be downloaded from Github.com/UVVM.

 

Bitvis is also a course provider.

  • ‘Accelerating FPGA design’ (2 days). A unique course in its focus on architecture, modularity, coding, CDC and Reuse.
  • ‘Advanced VHDL Verification – Made simple’ (3 days incl. labs). An intensive course on how to significantly reduce verification time and at the same time improve the quality – by making a better, easy to control and more understandable testbench architecture.