Code and Functional Coverage within a VHDL Test Environment

Code and Functional Coverage within a VHDL Test Environment

Web Seminar

Overview

Code coverage is the only verification metric generated automatically from design source in RTL or gates. While a high level of code coverage is required by most verification plans, it does not necessarily indicate correctness of your design. It only measures how often certain aspects of the source are exercised while running a suite of tests.

Functional coverage is user-defined coverage – in contrast with code coverage, which is automatically inferred from the source. At the most abstract level, functional coverage specifies some values to observe at certain times in a design or test bench, and counts how many times those values occur.

 

What You Will Learn

In this session you will learn with a sample VHDL test environment:

  • What is Code and Functional Coverage
  • How to collect Code Coverage
  • How to write and collect SystemVerilog Functional Coverage
  • How to efficiently analyze and report both of them

 

Timeline:

At the beginning of this session, you will get a 30 min introduction presentation about what is Code and Functional Coverage and how to efficiently analyze them.

 

After that you have the chance to walk through a 1 – 2 hours hands-on online workshop. The system for this workshop will be open until 5pm UTC+02:00 and you can do the lab within that time.

 

Pre-requisites:

For the introduction presentation:

  1. Registration
  2. Headset

 

For the online hands-on workshop:

  1. Registration with IP address (www.whatismyip.com)
  2. NoMachine Client (https://www.nomachine.com/download)
  3. 1 – 2 hours of your time

 

Details

What

Web Seminar: Code and Functional Coverage within a VHDL Test Environment

 

When

Thursday the 1st of June

 

Time

10:00 - 12:00 hr Europ/Berlin

 

Where

Online