FPGA World 2017

FPGAworld Conference 2017

Stockholm 19 September and Copenhagen 21 September


The Conference is an international forum for researchers (ACM), engineers, teachers and students/hackers. Complex heterogeneous SW/HW embedded systems, products, education&industrial cases and more based on FPGA technology. FPGAworld sponsor the academic&industrial tracks, lunches, premises, administrations etc. from sponsors and exhibitors.


Meet the InnoFour representatives at FPGA world in our exhibition booth or attend our presentation about Mastering Clock Domain Crossing challenges in FPGA Design.


Mastering Clock Domain Crossing challenges in FPGA Design:

Metastabilty from the intermixing of multiple clock signals is not modeled by simulation. Unless you leverage exhaustive, automated Clock Domain Crossing (CDC) analyses to identify and correct problem areas, you will inevitably suffer unpredictable behavior when you go to the lab or when the FPGA is used in the field. Bottom-line: automated CDC verification solutions are mandatory for multi-clock designs.


Designers increasingly use advanced multi-clocking architectures to meet the high-performance and low-power requirements of their chips. An RTL or gate-level simulation of a design that has multiple clock domains does not accurately capture the timing related to the transfer of data between clock domains. As a consequence, simulation does not accurately predict silicon behavior, and critical bugs may escape the verification process.


The Questa CDC Solutions identify errors that have to do with clock domain crossings – signals (or groups of signals) that are generated in one clock domain and consumed in another. It does so with structural analysis and recognition of clock domains, synchronizers, and low power structures (via UPF); and with generation of metastability models for reconvergence verification. The technology checks all potential failure modes and presents to the user familiar schematic and waveform displays. Additionally, in concert with simulation this technology can be used to inject metastability into functional simulation to verify the DUT correctly processes asynchronous clocks.




Date Sweden

September 19, 2017



ÅF Frösundaleden 2A , 169 70 Solna
Near the highway E4. Parking: is on the other side of the highway E4, Hagaparken



Please check this link to see the program on line


Date Denmark

September 22, 2017



DTU (SCION) Building 372 Diplomvej, 2800 Lyngby



Please check this link to see the program on line


28th of September TEC Lund 2017
26th of September PADS User Group 2017 - Sweden
19th and 21st of September FPGA World 2017
28th - 29th of November FloEFD Simulation Conference 2017