Calibre - Physical Design & Verification

IC Verification & Signoff Using Calibre

Mentor's IC verification and sign-off includes not only traditional rule-based physical verification and parasitic extraction, but also new capabilities and automated technologies that help improve yield by enhancing the design itself.

Calibre® is the overwhelming market share leader and the industry standard for IC physical verification, due to the outstanding performance, accuracy and reliability of Calibre products. Over the last two years, Calibre nmDRC™ has reduced average DRC runtime by a factor of five, while Calibre's innovative Hyperscaling and MTFlex™ technologies have cut memory requirements in half. Calibre nmDRC also reduced overall cycle time with incremental DRC, which allows designers to make DRC runs in parallel. As DRC violations are reported, designers can immediately fix and recheck just the affected areas, while the initial DRC run continues.

To handle complex and multi-variate, multi-dimensional checks that are not adequately addressed by traditional design rules, Calibre nmDRC's equation-based DRC (eqDRC) capability enables designers to express design rule checks as continuous, multi-dimensional functions that accurately and precisely reflect underlying physical interactions. With eqDRC, designers can use Calibre nmDRC to address complex DFM issues that other DRC tools simply can't handle.

Calibre nmLVS provides actual device geometry measurement, programmable electrical rule checking, and sophisticated interactive debugging capabilities to ensure accurate circuit verification and further improve the designer's productivity.


Features and Benefits

  • The underlying hierarchical processing engine ensures robust testing and implementation across all applications, while providing best-in-class runtimes.
  • Common design platform integration enables rapid deployment of all Calibre nm Platform applications into the user’s design environment.
  • Integrated scripting environment across all applications (SVRF and TVF) allow users to customize their design and verification environment to suit the specific and evolving needs of their design teams.
  • Hyperscaling technology brings superior scalability and lightning fast-run times for computationally intense applications, while reducing capital expenditures by extending the useful life of existing shared memory processor systems, and fully utilizing inexpensive distributed rack systems.


Physical Verification Products

Calibre's physical verification capabilities are the industry standard for accuracy, reliability, and performance. Learn More ►

Calibre nmLVS
The industry-standard physical verification tool for layout vs. schematic comparison combines accurate circuit verification with fast runtimes and interactive debugging.

 

Calibre nmDRC
The industry standard for design rule checking provides fast cycle times and innovative design rule capabilities

 

Calibre Interactive™
The Calibre Interactive™ invocation GUI provides users with fast and easy access to the Calibre® tool suite, enabling designers to perform physical verification and parasitic extraction from within their familiar IC design environment.

 

Calibre InRoute

Calibre InRoute enables designers to achieve signoff-quality manufacturing closure during physical design within the Olympus-SoC place and route system.

 

Calibre RVE™

Calibre RVE™ provides a graphical results viewing environment that can be used with all Calibre tools and popular design layout tools to reduce debug time by visually identifying design errors instantly in the user’s own design environment.

 

Calibre Pattern Matching

Calibre® Pattern Matching replaces text-based design rule checks with a visual geometry that ensures a precise and accurate implementation of the design specification.

 

Calibre DESIGNrev™
The Calibre DESIGNrev layout editor speeds full-chip design completions and tape-outs by rapidly loading, displaying and saving large GDSII and OASIS files.

 

Calibre InRoute

Calibre InRoute enables designers to achieve signoff-quality manufacturing closure during physical design within the Olympus-SoC place and route system.

 

Calibre Automatic Waivers

Calibre® Automatic Waiver provides automated recognition and removal of waived design rule violations during DRC. Calibre Automatic Waivers eliminates costly time and effort from the verification process, and ensures accurate processing of all waiver information on every DRC run. .

  

Calibre RealTime

Calibre® RealTime enables on-demand Calibre signoff design rule checking (DRC) for custom and analog/mixed-signal design flows, improving both design speed and the quality of results by providing immediate feedback on design rule violations and recommended rule compliance. 

 

Circuit Verification Products

Calibre's circuit verification strategies and tools effectively and efficiently address the reliability and functional yield challenges of today’s advanced and complex IC designs. Learn More ►

Calibre nmLVS
The industry-standard physical verification tool for layout vs. schematic comparison combines accurate circuit verification with fast runtimes and interactive debugging.

 

Calibre xRC
Calibre xRC™ offers a robust parasitic extraction tool that delivers accurate parasitic data for comprehensive and accurate post-layout analysis and simulation.

 

Calibre xL
Full-chip, fast, and accurate extraction of frequency dependent loop inductance and loop resistance and automatically accounts for return path change with frequency. Fully integrated with Calibre nmLVS and xRC.

 

Calibre PERC
Industry’s only programmable electrical rule checking (PERC) tool designed to address advanced verification requirements to ensure optimal design yield and improve reliability.

 

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