PCB Design Perfection Starts in the CAD Library - Part 5

Part 5 - PCB Design Perfection Starts in the CAD Library

SOT23 (Small Outline Transistor) Components

 

The SOT23 is the most popular of the SOT component families. It has 3-, 5-, 6- and 8-pin variations and three popular pin pitches. Note: All pictures are shown in the “Nominal Environment” land pattern.

 

Figure 1

  Figure 1 illustrates 0.5 mm pitch SOT23 3-pin and 8-pin examples
     

 

0.5 mm Pitch SOT23 Fanout Examples

Figure 2 illustrates four different 0.5mm pitch 3-pin SOT23 land pattern via fanout techniques. The SOT23 parts are placed on a 0.5 mm grid system and all the vias snap to a 1.0 mm grid.

 

Figure 2

 
  • There are two 0.1 mm trace/space technology on all layers.
  • Via land size is 0.5 mm, hole size is 0.25 mm and plane anti-pad is 0.7mm.
   

     

    0.5 Mm Pitch SOT23 Fanout Examples

         

    Figure 3

      Figure 3 illustrates four different 0.5mm pitch 8-pin SOT23 land pattern via fanout techniques. The SOT23 parts are placed on a 0.5 mm grid system and all the vias snap to a 1.0 mm grid. This allows two 0.1 mm trace/space technology on all layers.
         

     

     

    Figure 4

      Figure 4 illustrates 0.65 mm pitch SOT23 3-, 5-, 6- and 8-pin examples.
         

     

    0.65 mm Pitch SOT23 Fanout Examples

    Figure 5

      Figure 5 illustrates five different 0.65mm pitch 3-, 5-, 6- and 8-pin SOT23 land pattern via fanout techniques. The SOT23 parts are placed on a 0.5 mm grid system and all the vias snap to a 1.0 mm grid. This allows two 0.1 mm trace/space technology on all layers with 0.5 mm via land.
         

      

     

    Figure 6

      Figure 6 illustrates 0.95 mm pitch SOT23 3, 5, 6 and 8-pin examples.
         

     

    0.95 mm Pitch SOT23 Fanout Examples

         

    Figure 7

      Figure 7 illustrates seven different 0.95mm pitch 3, 5, 6 and 8 pin SOT23 land pattern via fanout techniques. The SOT23 parts are placed on a 0.5 mm grid system and all the vias snap to a 1.0 mm grid. This allows two 0.1 mm trace/space technology on all layers.
         

     

    The SOT component family uses a gull wing component lead. All gull wing leaded components have four different sets of land pattern rules. These examples are for the “Nominal Environment”.

    1. Pin pitch less than 0.625mm (side goal is -0.02 mm) considered “fine pitch”
    2. Pin pitch greater than 0.625 mm (side goal is 0.03 mm)
    3. Outward flat ribbon with pin pitch less than 0.625mm (heel goal is 0.15 mm and side goal is -0.02 mm)
    4. Outward flat ribbon with pin pitch greater than 0.625mm (heel goal is 0.15 mm and side goal is 0.03 mm)

     

    The formula that calculates the difference between gull wing and outward flat ribbon (mini gull wing) is shown in Figure 8.

     

     

    Figure 8

     

    We already discussed chip and molded body assembly outlines and ref des in the last column. It’s important to note that the lands (pads) do not get added to the assembly drawing layer for small parts. The two most important things on the assembly drawing are the Ref Des and Component Outline. If the part is too small and the lands interfere with the Ref Des, then do not add the top assembly lands to the padstack. However, if the lands do not interfere with the Ref Des then we should add the top assembly lands to the padstack.

     

    Here are some of the various assembly outlines for the 0.95 mm pitch SOT23 component family. See Figure 9 for the 3-, 5- and 6-pin versions of the assembly outline, Ref Des, polarity marker for pin 1 location and lands (pads).

     

     

    Figure 9

     

    There are a number of silkscreens outlines for the various SOT component families; Figure 9 illustrates several of them.

     

    See this figure (10) for the SOT23 silkscreen outline, polarity marker and 0.5 mm post assembly inspection dot for pin 1 location and lands (pads). In this case the silkscreen outline is too narrow for an adequate polarity marker inside the outline, so the post assembly inspection dot for pin 1 will have to be sufficient.

     

    Coming Up

    Additional brief topical articles will appear in future newsletters. You can also read more detail in my blog, which can be found at:http://blogs.mentor.com/tom-hausherr/

     

    Written by Tom Hausherr CID+

    EDA Library Product Manager

    Mentor Graphics Corporation

    Reprinted by permission from iConnect007