Olympus-SoC

Olympus-SoC

Solving 65 nm and 45 nm Design Challenges

 

The Olympus-SoC™ IC implementation solution is purpose-built to address the performance, capacity, time-to-market, and variability challenges at advanced nodes. With full support for low-power design styles, signoff-quality timing analysis and optimization, and DFM-aware routing, Olympus-SoC delivers the highest quality layouts with fast turnaround and rapid closure

 

 

Advanced Support for Low Power

The Olympus-SoC low power platform comprehensively handles the requirements of low-power design. It ensures optimization of the overall solution without excessive iterations, enabling engineers to rapidly deliver fully-optimized, power-efficient designs.

 

Olympus-SoC provides seamless concurrent optimization for both power and timing, covering all operating modes and process corners through all stages of the flow. It completely automates multi-supply-voltage design flows with automatic power grid routing for multiple voltage supplies, support for Dynamic Voltage and Frequency Scaling (DVFS) to handle varying supply voltages and clock frequencies, and auto placement and routing of special cells such as level shifters, isolation cells, and MTCMOS switches. Olympus-SoC also provides concurrent multi-Vt optimization, power gating, retention flop synthesis, support for gas station methodology, and power-aware buffering and sizing.

 

To reduce dynamic power, Olympus-SoC provides automatic power-aware clock tree synthesis (CTS) with smart clock gate placement, slew shaping, register clumping and concurrent MCMM optimization, ensuring a balanced clock tree with the minimum number of clock buffers.

 

Olympus-SoC supports the Unified Power Format (UPF) throughout the netlist-to-GDSII flow, including the ability to describe design intent through power state definition tables. The ability to process 100 million + gates in flat or hierarchical modes provides better, faster chip assembly and full-chip power optimization.

 

Best Quality-of-Results in Physical Design

Olympus-SoC delivers concurrent optimization of timing, signal integrity, die size, leakage and dynamic power across all design and process corners throughout the design flow. It automatically analyzes manufacturing variability issues and drives optimizations throughout the implementation, starting with floor planning, and continuing through feasibility, placement, optimization, clock tree synthesis, and routing.

 

The next-generation routing architecture incorporates variation-aware timing optimization and litho-modeling to address DFM and OPC effects early in the design cycle. Early DFM analysis allows Olympus-SoC to provide a high correlation with industry-standard timing and physical verification sign-off tools. 

 

Shorter Turnarounds and Faster Design Closure

Olympus-SoC’s ultra-compact database provides the industry's highest capacity and smallest memory footprint, allowing it to handle 100 million + gate designs. The patented “virtual timing graph” architecture enables Olympus-SoC to handle any number of timing views of the design with minimal impact on runtimes and memory requirements. Patent-pending physical synthesis technology gives highly-optimized results for multi-million gate flat designs in a single overnight run. New advances in performance bottleneck detection and analytical optimization address the complex challenge of constraint validation for "dirty" design data, providing robust optimization in the presence of ill-formed constraints.

 

Sign-off quality timing, extraction, and delay calculation are native to the Olympus-SoC kernel. Fully-multithreaded analysis engines and the industry’s only fully-parallelized timing and optimization engine slash run times by efficiently using the latest platforms, providing a 7x speedup on an 8-CPU machine. The combination of these features allows Mentor customers to achieve design closure on large complex designs in a fraction of the time required for existing design flows. Olympus-SoC customers are experiencing 2-3X faster design closure times in addition to an additional 30% power savings versus traditional tools.

 

Olympus-SoC datasheet

 

 

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