HDL Designer Series

Dates

This course is not yet planned.

HDL Designer Series

 

Duration: 2 Days
Course Part Number: 209128

Description
The HDL Designer course was developed to teach you to use HDL Designer Series effectively in your FPGA or ASIC design process. The lecture takes you through the HDL Designer Series design flow. This includes modeling the design with both graphics and text, generating HDL, and then simulating and animating the design to verify behavior.
Detailed lab exercises help reinforce what is discussed during the lectures and provide you with extensive tool usage experience under the guidance of our industry expert instructors.

You will learn how to

  • Set up libraries to hold your designs
  • Model hierarchy and connectivity using block diagrams and IBD
  • Model finite state machines with state diagrams
  • Model sequential processes with flow charts
  • Model combinatorial circuits with Truth Tables
  • Create and edit component symbols
  • Generate HDL for your graphical/textual design
  • Compile your design for simulation
  • Simulate your design using ModelSim
  • Animate and debug your design
  • Reuse components
  • Convert existing HDL designs into graphical/textual HDL Designer Series designs
  • Create test benches
  • Manage your design using version management
  • Ensure your design meets required design rules using DesignChecker
  • Interface with a wide range of downstream tools (compilers, simulators, and synthesis tools)
  • Trace requirement references between ReqTracerTM and HDL Designer


Hands-On Labs

Throughout this course, extensive hands-on lab exercises provide you with practical experience using HDL Designer Series software.

  • Import existing HDL code into HDL Designer
  • Create block diagrams, state machines, truth tables, and flow charts
  • Create control logic using state machines
  • Generate HDL for your design
  • Create a test bench using a flow chart to provide stimulus
  • Compile and simulate your design
  • Troubleshoot your design using animation
  • Place existing design elements into new designs
  • Implement Altera MegaWizard and Xilinx CoreGen components in your design
  • Import existing HDL design hierarchy into HDL Designer for visualization
  • Run DesginChecker and analyze results

  • Generate HTML documentation


Audience

  • FPGA and ASIC Designers
  • CAD Engineers and Managers who will be responsible for integrating HDL Designer Series into their design flow.
  • Members of CAD support groups who are responsible for increased productivity of FPGA and ASIC design teams.


Prerequisites

  • Basic knowledge of FPGA and ASIC and design techniques and procedures
  • Reading knowledge of HDL languages (VHDL or Verilog)
  • Familiarity with Windows or Linux/UNIX operating systems

 

Guides

Student workbook table of contents


For more information:

 

InnoFour BV

Twentepoort Oost 61-02
7609 RG ALMELO
The Netherlands
tel +31 546 454 530
fax +31 546 453 006
training@innofour.com