Calibre Fundamentals: Writing DRC/LVS Rules

Dates

This course is not yet planned.

Calibre Fundamentals: Writing DRC/LVS Rules

 

Duration: 4 days

Course Part Number: 058450

 
Description
This course will teach you to effectively write and maintain Calibre nmDRC and nmLVS rule decks for your semiconductor processes. In this class, you will extensively study the Standard Verification Rule Format (SVRF) language used in Calibre rule decks. The lecture modules will guide you through the various concepts underlying state-of-the-art layout verification techniques and specific aspects of the Calibre toolset. Hands-on lab exercises will reinforce lecture topics and provide you with rule writing experience under the guidance of our industry expert instructors.

The lecture modules will guide you through the various concepts underlying state-of-the-art layout verification techniques and specific aspects of the Calibre toolset. Hands-on lab exercises will reinforce lecture topics and provide you with rule writing experience under the guidance of our industry expert instructors.

You will learn how to

  • Write DRC rules that perform a full complement of layout dimensional checks
  • Write specification statements to control DRC output
  • Use Boolean and topological operators to derive new layer data
  • Debug rule files
  • Write polygon-directed and edge-directed checks
  • Write basic and enhanced antenna rule checks
  • Improve DRC run-time efficiency
  • Write equation-based DRC rule checks
  • Create and use layer properties
  • Write rules to establish layout connectivity
  • Write rules to recognize different devices such as MOS transistors, resistors and capacitors of different types, bipolar transistors etc. in the layout
  • Extend the set of built-in device templates to include your own custom devices
  • Extract various properties such as width, length, resistance and capacitance of recognized devices, using the Built-in property language within Calibre nmLVS TM and compare these values with those specified in the source netlist
  • Effectively utilize the text present in the GDSII layout database, and supplement it with text supplied through the rule file to annotate nets and ports • Optimally use the various Calibre statements that deal with net and port names in the layout
  • Write various LVS specification statements that control how the layout netlist extracted from the layout database is compared to the source netlist
  • Effectively block out selected cells during the LVS netlist comparison process
  • Call Calibre TVF routines from within device property computation functions
  • Access layout property data from within device property computation functions
     

Hands-On Labs
Throughout this course, extensive hands-on lab exercises provide you with practical experience in using Calibre under the guidance of our expert instructors. Hands-on lab topics include:

  • Preparing the Rule File and Running Calibre
  • Viewing DRC and LVS Results
  • Using the Online Documentation
  • Writing Layer Definitions
  • Writing DRC and LVS Specification Statements
  • Writing and Testing Dimensional Rule Checks
  • Designing and Testing Derived Layer Statements
  • Writing Polygon-directed Rule Checks
  • Designing and Testing Edge and Error-directed Rule Checks
  • Creating and Using Layer Properties
  • Writing and Testing Connectivity Statements
  • Designing and Testing Antenna Rule Checks
  • Taking Advantage of Hierarchy
  • Setting LVS Report Options
  • Finding Soft Connections
  • Creating and Naming Ports
  • Inserting Text Objects Into a Layout Using the Rule File
  • Writing Device Recognition Statements
  • Specifying Custom User-Defined Devices
  • Using the Built-In Language to Define Device Properties
  • Writing TVF code to generate a DRC rule file


Intended for

  • Experienced IC Layout Engineers and Layout Verification specialists who will write, maintain, support, and optimize various DRC and LVS rule decks in their organization
  • Experienced CAD Engineers and Managers who will be responsible for integration of the Calibre toolset in their design flow
  • Experienced CAD specialists who interface with various foundries (such as TSMC, UMC, Chartered) and integrate the rule decks supplied by these foundries into the verification flow
  • Layout Verification specialists in foundries who are responsible for generating qualified rule decks for their various process offerings


Prerequisites

  • Completion of the Calibre nmDRC/nmLVS class is very highly recommended
  • Thorough knowledge of IC layout techniques and procedures
  • Experience with an IC layout editing tool
  • Good understanding of SPICE netlists
  • Familiarity with UNIX
  • Good understanding of layout verification concepts and experience with layout verification tools

 

Guides

Student workbook table of contents

 

For more information:

InnoFour BV
Twentepoort Oost 61-02
7609 RG ALMELO
The Netherlands
tel +31 546 454 530
fax +31 546 453 006
training@innofour.com