Emulation Systems

The Veloce SoC verification system reduces project schedule and cost risk through simulation acceleration and high performance in-circuit emulation. The Veloce product line supports the Open Verification Methodology (OVM) and Assertion-based Verification (ABV).

Value is delivered by:

  • Accelerating transaction-based and signal-level block and full SoC regression test runs by 100s to 1000s of times,
  • Providing a comprehensive, simulation-like debug environment
  • Providing a hardware platform for software development and debug months before first silicon is available,
  • Enabling full system integration using real-world data and software for test benches before first silicon availability,
  • Accelerating post-silicon validation by accelerating regression tests before committing changes to silicon, and
  • Eliminating most silicon re-spins due to functional errors.

 

The Veloce simulation acceleration/emulation product line has five scalable hardware configurations that can be configured to verify designs from 8 million gates up

to 512 million gates within a single chassis.


 

 

Comprehensive Verification Environment
Veloce Systems have complementary software and application solutions to provide a comprehensive verification environment.

HDL Link Software provides a mixed-level modeling, co-simulation interface for Veloce and the Questa simulator, and other commercial simulators. HDL Link also enables ultra-fast simulation acceleration by automatically encapsulating simulation test benches in a C/C++ environment for regression testing using Veloce.

iSolve Application Solutions provide complementary solutions for memory modeling, embedded processors, software debug, multi-media data streaming and analysis and industry standard bus and communications interfaces.
 

Veloce Product Family

Veloce
High-performance, high-capacity hardware-assisted solution for verifying embedded systems and SoC designs

 

TestBench XPress
TestBench XPress (TBX) is the Veloce co-modeling software application that makes the Veloce SoC verification system a transaction-level modeling(TLM) verification engine running up to 10,000x the speed of TLM software simulators.

 

HDL Link
HDL Link Software is an application that enables the Veloce system (1) to run in a mixed-level modeling, co-simulation mode with the Questa simulator and (2) to accelerate block-level and full SoC regression test runs by 100s of times in a free running acceleration mode (fast regression database mode-FRDB).

 

iSolve
The iSolve family of application solutions consists of flexible, pre-configured software models and specialized hardware sub-systems for the Veloce product family. These models and sub-systems address the SoC modeling and real world testing requirements that are required for you to quickly build complete, high performance SoC verification environments.

 

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