Products A to Z - Functional Verification
0-In Clock-Domain Crossing
Designers increasingly use advanced multi-clocking architectures to meet the high-performance and low-power requirements of their chips. The 0-In® CDC verification solution focuses on the interaction between these clock domains.
0-In Formal Verification
The 0-In® Formal verification solution offers the highest capacity and performance available to help you find your most complex bugs.
Certe Testbench Studio
Certe Testbench Studio delivers a powerful, yet familiar, environment that enables the rapid creation and complete understanding of OVM and SystemVerilog-based testbenches for complex ASIC and FPGA designs.
FormalPro
FormalPro is the Mentor Graphics high-capacity equivalence checking solution for regression testing of ASICs and ICs. FormalPro uses formal verification techniques to prove that a design is equivalent to its golden reference model.
HDL Designer
HDL Designer provides engineers with a suite of advanced design editors to facilitate development: interface-based design spreadsheet editor (IBD) and block diagram, state-machine, truth table, flow chart and algorithmic state-machine editors.
HDL Link
HDL Link Software is an application that enables the Veloce system (1) to run in a mixed-level modeling, co-simulation mode with the Questa simulator and (2) to accelerate block-level and full SoC regression test runs by 100s of times in a free running acceleration mode (fast regression database mode-FRDB).
ICanalyst CB
The ICanalyst CB verification flow available in Mentor's ICanalyst™ is a batch and interactive platform for automating the verification of complex analog and mixed-signal System-on-Chip designs.
inFact
inFact testbench synthesis provides a straightforward way to achieve higher coverage, while significantly reducing input code required to write a testbench.
iSolve
The iSolve family of application solutions consists of flexible, pre-configured software models and specialized hardware sub-systems for the Veloce product family. These models and sub-systems address the SoC modeling and real world testing requirements that are required for you to quickly build complete, high performance SoC verification environments.
ModelSim
ModelSim SE (Special Edition) is our UNIX, Linux, and Windows-based simulation and debug environment, combining high performance with the most powerful and intuitive GUI in the industry.
Questa
Questa is Mentor Graphic's Advanced Verification Environment and is the only integrated verification platform that can improve quality, productivity, and predictability for any verification flow.
Questa ADMS
Questa ADMS is a language-neutral, mixed-signal simulator that enables top-down design and bottom-up verification of multi-million gate analog/mixed-signal system-on-chip designs.
Questa Codelink
Questa Codelink is a graphical source-level debugger for code executing on RTL processor models from ARM and MIPS.
Questa MVC
With the pre-verified, configurable, and reusable verification components in the Questa MVC library, you can reduce the overall testbench development effort and free up time for testing your proprietary modules and functions.
Seamless
Seamless enables users to debug hardware/software integration issues early in the design cycle by running embedded software on a simulation model of the embedded hardware.
Semiconductor & IP Development
Semiconductor & IP Development
TestBench XPress
TestBench XPress (TBX) is the Veloce co-modeling software application that makes the Veloce SoC verification system a transaction-level modeling(TLM) verification engine running up to 10,000x the speed of TLM software simulators.
Veloce
High-performance, high-capacity hardware-assisted solution for verifying embedded systems and SoC designs
Veloce-based In-circuit Emulation
To accommodate the increasing complexity of today’s SoC designs many design teams are moving to high-level design languages, like System Verilog and System C, and transaction-level modeling for test benches to speed up their development and functional verification efforts.
Veloce-based Simulation Acceleration
Veloce-Based Simulation Acceleration speeds up block-level and full SoC regression test runs by 100s to 1000s of times, (1) during block and full SoC RTL development and (2) post-silicon validation by accelerating post-change regression tests.
Vista Architect
Vista™ Architect, a superset of the Vista Design solution, is a complete TLM 2.0-based solution for architecture design and exploration enable system architects and SoC designers to make viable architecture decisions, prototype and analyze complex systems.
Visual Elite
Visual Elite™ is the state-of-the-art design and integration platform enabling designers and system architects to intuitively capture and connect SystemC, TLM 2.0 and HDL blocks into complex SoC’s and systems.
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