Questa ADMS
Questa ADMS™ is a language-neutral, mixed-signal simulator that enables top-down design and bottom-up verification of multi-million gate analog/mixed-signal System-on-Chip designs.
The Mentor Graphics Questa ADMS™ simulator gives designers a comprehensive environment for verifying complex analog/mixed-signal (AMS) System-on-Chip (SoC) designs. ADMS combines four high performance simulation engines in one efficient tool: Eldo™ for analog large-signal and frequency domain simulations, ModelSim® for digital simulations, Mach™ for fast transistor-level simulations and Eldo-RF™ for modulated steady state simulation. ADMS is fully integrated with the Mentor Graphics Design Architect-IC™ (DAIC) tool, the Cadence® Analog Design Environment, and the ModelSim graphical interface. The CommLib™ QuickStart™ library of essential telecommunication blocks jumpstarts your development of system level designs and exploration of architectural variations. The TCL scripting language enables batch control of the simulation.
Features and Benefits
- Enables top-down design and bottom-up verification of multi-million gate AMS SoC designs
- Lets designers choose their own language and simulation algorithm combinations
- Saves time and boosts productivity by combining proven, industry-leading simulation technologies, and supporting a variety of languages
- Builds on previous design investments through its design flow integration with Mentor Graphics Design Architect-IC and Cadence Analog Design Environment
- Empowers high-level, system-level design, architectural exploration, and rapid learning of behavioral modeling techniques
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