ICassemble

As the digital content in today's mixed-signal SoC designs continues to grow, top-level floor planning and routing is becoming an increasingly important component of the design flow. To address the complexities of analog/mixed-signal chip assembly, Mentor Graphics developed ICassemble, which provides a robust set of features for floor planning, top-level assembly and interactive routing.

Features and Benefits

Advanced floor planning features:

•  Layout wire propagation (push/pull through hierarchy with connectivity)
• Simple hierarchy management
• ECO flow integration
• Top-down block boundary editing ability
• Input from Design Architect-IC schematic, SPICE netlist, Verilog netlist
• Read/write LEF/DEF blocks

Interactive routing capabilities:

• Truly integrated routing technology with pushing for "routing in place"
• Flexible blockage control
• On-the-fly visual feedback of length, resistance, capacitance, or costing
• Intelligent minimization of nets being pushed
• Multiple bus routing modes
• Shielded wires
• Mirrored and differential pair routing
• Controlled wire handling for timing closure
• Supported post-routing functions:
• Via minimization
• Layer swapping
• Wire bend reduction

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