Olympus-SoC Digital IC Design

Delivering Innovative Technologies for Fast & High-Quality Design Closure at Advanced Process Nodes
Mentor's physical layout solution, Olympus-SoC, delivers innovative technologies to solve the power, performance, capacity, time-to-market, and variability challenges encountered at the leading-edge process nodes.

The Olympus-SoC netlist-to-GDSII system performs variation- and power-aware rapid feasibility, including placement, advanced clock tree synthesis, and optimization. It also includes litho-driven routing that addresses optical proximity correction (OPC), resolution enhancement technology (RET), and critical area analysis (CAA) early in the design cycle, ensuring faster timing closure for complex process rules.

Benefits of Olympus tools:

• Boost IC performance with advanced multi-corner, multi-mode (MCMM) optimization
• Reduce power consumption in clock trees with MCMM clock tree synthesis
• Improve yield with DFM-aware routing to address lithography issues in a timing context during implementation
• Speed time-to-market with fewer design iterations, scalable multi-threading, and sign-off quality closure
• Load and process designs of 100M gates or more with the industry's highest-capacity data structure
• Reduce costs through high yields and fast time-to-market Boost IC performance with advanced multi-corner, multi-mode (MCMM) optimization

Digital IC Design Products

Olympus-SoC is a complete IC design-for-variability implementation solution targeted at 65nm/45nm designs.

Manufacturing Variability Solutions

Creating chips with high functionality, multiple operating modes, low power consumption and extreme reliability—pushing the manufacturing process to the limit. But your advanced ICs are increasingly sensitive to the smallest manufacturing variations, and that affects both performance and yield.

Simply increasing guard bands does not effectively deal with variability…and it diminishes your competitive advantage. How do you deal effectively with variability and maintain your competitive edge in a nanometer world? Mentor Graphics has answers to your most challenging questions.

Manufacturing Variability Solutions ►

Low Power Solutions

These days everyone is concerned about power consumption. And while you’d like to tackle power as early in the design process as possible, at the end of the day it’s about balancing power with existing requirements of system functionality, performance, and manufacturability.

The Unified Power Format (UPF) provides the backbone to our low power technologies so engineers can define power based architectures, create power aware strategies, and verify low power designs throughout the TLM to GDSII flow.

Low Power Solutions ►

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