SystemVerilog Assertions (SVA) - Kista (Sweden)

Duration: 1 Day

Pricing: 650 EUR

Course Part Number: 230782

Description

This course serves either as an add-on to Mentor graphics’ SystemVerilog for Verification course or as a stand-alone one day class for those with experience in SystemVerilog who wish to become proficient using SystemVerilog Assertions (SVA) for assertion based verification.

Hands-On Labs

Throughout this course, extensive hands-on lab exercises provide you with practical experience using Questa software.

Audience

Design Engineers

Verification Engineers

Prerequisites

Recent attendance in a SystemVerilog for Verification class

Course Outline

• Immediate assertions
• Concurrent assertions basics
• Boolean expressions
• Sequences
• Property block
• Verification directives
• Sequence blocks
• Sequence operators
• Repetition operators
• Other methods and operators
• Sequence Expressions
• Property block
• Operators
• Data use
• Verification directives
• Bind directive
• Clocks
• Multiple clocks

For more information:

InnoFour Scandinavia

Kvarnstugevägen 28

13336 Saltsjöbaden

Sweden

tel +46 730 308 150

training@innofour.com