Web Seminar: Simplify FPGA Design with VHDL-2008

Simplify FPGA Design with VHDL-2008

Live Web Seminar

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Overview

VHDL has long been known as a verbose language and “strongly typed”. VHDL-2008 introduces various constructs with simplified syntax, and thus making it easier to use. While many may consider the changes and additions for VHDL-2008 good for only simulation; synthesis, too, reaps tremendous benefits from the new changes in the language standard. The amount of coding to get the same results has been reduced, the readability and reusability of the HDL has been increased, and complex structures are easier to implement without complex coding deployments.

 

Please join us in our brief webinar exploration of how VHDL-2008 can not only help simplify your HDL coding, but also help improve your overall design implementation.

 

What You Will Learn

  • Better HDL coding style
  • Efficient design optimization

 

Who Should Attend

  • Design engineers
  • Engineering managers

 

Products Covered

 

Details

What Simplify FPGA Design with VHDL-2008
When Thursday the 22nd of May 2014
Where Online
Time 15.00 - 16.00 hr
Registration Web