Attention FPGA Designers
Attend this free online session to learn how Questa Formal with Autocheck and Clock Domain Crossing (CDC) can provide you with the needed solution to achieve your verification goals.
Mentor Graphics, together with our partners InnoFour, Saros and TRIAS, invite you to attend this online seminar on the following date:
Tuesday November 15.
Learn how to rapidly identify, debug and fix logic, functional and CDC related issues in your design.
Stefan Bauer
Stefan joined Mentor Graphics in 2014 for supporting the distribution channel in the whole HDL area with focus on functional verification. Prior to that, Stefan worked as a verification engineer for Ericsson in Nuremberg, Germany. The main focus of his work was verifying parts of an ASIC by using an OVM/UVM test environment. Stefan has a master’s degree in Electrical Engineering from the Friedrich-Alexander-University Erlangen-Nuremberg.
When
Tuesday the 15th of November 2016
14:00 - 15:00 CEST
EDA
Electrical & Wire Harness Design
Electronic System level Design
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