Advanced VHDL Verification - Made simple

Dates

This course is not yet planned.

Advanced VHDL Verification - Made simple

Efficiency and quality is all a question of overview, readability, extensibility, maintainability and reuse, - and a good architecture is the answer. This applies for both Design and Verification.

 

Presented by Espen Tallaksen, Bitvis AS

Location: Circle Consult in Nærum, Rundforbivej 271A Denmark.

 

Description

On average half the development time for an FPGA is spent on verification. It is possible to significantly reduce this time, and major reductions can be accomplished with minor adjustments. This is an intensive 3-day course on how to reduce development time and at the same time improve the quality.

 

The main differentiators between this and other similar courses are the focus on simplicity and the very structured approach to reuse - also inside a single project. We have seen and heard of many complex testbenches by various designers. A major problem with most of these testbenches seems to be that it gets too complex for everybody apart from the VHDL expert who designed it, – sometimes a person with a far more than average interest in the language or system details.

This course is based on the principles of ‘maximum cohesion & minimum coupling’ and ‘Divide and Conquer’, where the test case writer doesn’t have to know anything about the testbench implementation details, and the testbench implementer has a structured architecture all the way down. This approach to VHDL testbenches typically leads to man-hour savings of 20-60% and more, and is unique for this course.

 

A complete description of the course can be found here.

 

What you will learn

It is actually possible for almost all companies to speed up the FPGA verification and at the same time improve the FPGA quality and fault coverage. Learn how to build your testbenches in a structured way, which is the key to overview, readability, extensibility, maintainability and reuse. Theory is mixed with practical examples and handson tutorials. The course will also cover important general verification issues like:

  • Using sub-programs and various important VHDL constructs for verification
  • Handling simple verification in a simple manner
  • Making self-checking testbenches
  • Using logging and alert handling
  • Applying standard checkers for value and stability, and for waiting with a timeout for events
  • Using simple procedure based transactions like uart_transmit() and avalon_read() for simple verification scenarios
  • Making your own Bus Functional Model (BFM) – and adding features to speed up verification and debugging
  • Getting a kick start on BFMs with UVVM’s open source BFMs for Avalon, AXI4-lite/stream, UART, SPI, I2C, etc.  Making directed or constrained random tests – and knowing where to use what - or a mix
  • Learning to use the most important features from OSVVM for randomization and functional coverage
  • Applying coverage driven tests in a controlled manner
  • Using verification components and advanced transactions (TLM) for complex scenarios
  • Target data and cycle related corner cases and verifying them
  • Learning to use UVVM to speed up testbench writing and the verification process
  • Getting a kick start on your testbench by using available UVVM Verification components for AXI4-lite, AXI4-Stream, Avalon MM, SBI, SPI, I2C, UART; - and use these as templates for your own VVCs
  • Making a new UVVM Verification component in 30 minutes
  • Making an easily understandable and modifiable testbench even for really complex verification – and do this in a way that even SW and HW developers can understand them.

 

UVVM with OSVVM – The best of both worlds

UVVM (Universal VHDL Verification Methodology) and OSVVM (Open Source VHDL Verification Methodology) are both open source VHDL Verification Methodologies and Libraries. UVVM in combination with constrained random and functional coverage from OSVVM combines the best of two worlds into the ‘Unified VHDL Verification Methodology’ including:

  • the most important UVM functionality, but extremely simplified for the user,
  • the modular approach of a good FPGA design, with a hierarchical testbench structure that mirrors the design structure
  • a standardised VHDL testbench architecture and a standardised VHDL Verification Component architecture
  • a pure VHDL approach, where the user can just pick the functionality needed from well documented VHDL libraries, and e) the lowest possible user threshold for the functionality you need

 

UVVM will be used as example throughout the presentations and labs, but the principles taught and shown are general state of the art VHDL verification methodology. OSVVM will be used as example for constrained random and functional coverage. Examples will also show how OSVVM can be used as is inside and in parallel with UVVM. Hence you get basically 3 courses in one:

  • General VHDL verification course with best practices for making good testbenche
  • UVVM course – enabling the best possible VHDL testbench infrastructure and architecture
  • OSVVM course – showing you how to use the powerful randomisation and functional coverage

 

More info can be found here.