HyperLynx solution with industry-first automated and intelligent channel extraction for SerDes interface

Mentor announces HyperLynx solution with industry-first automated and intelligent channel extraction for SerDes interfaces

Mentor, a Siemens business, today announced its new HyperLynx® printed circuit board (PCB) simulation technology for high-performance designs, now providing the industry’s first end-to-end fully automated serializer/deserializer (SerDes) channel validation solution. Today’s advanced electronics products require intelligent high-speed design tools to ensure that designs perform as intended. With signaling rates of 50 Gbps becoming commonplace, and protocols like Ethernet, pushing 400 Gbps bandwidth, traditional methods are insufficient. This is crucial for industries that demand superior high-speed performance such as automotive, networking, data centers, telecom, and IoT/cloud-based products.

 

SerDes refers to the interfaces like PCI Express (PCIe) that are used anywhere high-bandwidth is required. However, today’s hardware engineers lack time to fully understand the detailed signal integrity requirements of these interface protocols and may have limited access to signal integrity (SI) and 3D EM experts for counsel. Mentor’s new HyperLynx release provides tool-embedded protocol-specific channel compliance— the industry’s first fully automatic validation tool for PCB SerDes interfaces. This includes a 3D explorer feature for design and layout optimization of non-uniform structures like breakouts and vias.

 

Mentor customer Sintecs, an electronic design service (EDS) company based in The Netherlands, specializes in complex board design and analyses. They developed the European-funded multi-board dReDBox, a completely new concept for a “data center in a box,” with disaggregate processing and memory resources connected with high-speed links (www.dredbox.eu). Using the HyperLynx DDRx Wizard and new SerDes Compliance Wizard, Sintecs could quickly explore the available design space to converge on a physical implementation that met industry standard compliance metrics for their product’s DDR4 (running at 2666 MT/s) and many PCIe3 interfaces. The new HyperLynx intelligent channel extraction tool helped compress the SerDes interface design schedule by automating the entire channel decomposition and modeling design task. Automated channel extraction was substantially faster than Sintecs’ previous manual method that required time from a 3D full-wave solver expert to model each channel discontinuity.

 

“We've successfully used HyperLynx to achieve the ‘first-time-right’ implementation of our high-speed DDR4 and PCIe SerDes interfaces for the dReDBox project,” stated Hans Klos, managing director of Sintecs B.V. “We’ve changed our way of working, and now our hardware designers and SI engineers use the SerDes Compliance Wizard to quickly iterate during interface design optimization, and final interface compliance verification.”

 

Protocol-specific Channel Compliance
Using the new HyperLynx release, hardware engineers can easily perform protocol-specific compliance checks. The tool provides embedded protocol expertise for PCIe Gen3/4, USB 3.1, and COM-based technology for Ethernet and Optical Implementers Forum (OIF). Engineers can easily perform equalization optimization (CTLE, FFE, DFE) based on protocol architecture and constraints.

 

“As data rates in high speed serial links increase, designing channels with acceptable bit error ratios, limited by equalization settings within a protocol’s range, requires a higher level of expertise. The new automated channel analyzer from Mentor is like having an expert on your shoulder. Running the analysis of a design before sign-off will catch many materials, vias and transmission line problems before they sneak into the final design,” said Eric Bogatin, dean of the Signal Integrity Academy and director of the Teledyne LeCroy Front Range Signal Integrity Lab. “And, for the final channel, the new compliance analyzer will recommend the optimized equalization settings to meet the protocol’s constraints. These innovations will help all hardware engineers sleep better at night.”

 

HyperLynx 3D Explorer
The 3D Explorer feature provides channel structure design and pre-layout optimization. Template-based 3D structure synthesis can be used for differential pair, BGA breakouts, via configurations, series-blocking capacitors, and more.

 

Product availability
The new HyperLynx release with automated SerDes channel validation will ship at the end of February 2018.

 

Contact us for more information by telephone or email.

 

 

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