Clock-Domain & Reset-Domain Crossing Verification

Why Reset Domain Crossing Verification is an Emerging Requirement to Accelerate Design-to-revenue in ASIC Developments

Overview

The design of quality clock-domain crossings (CDCs) today is aided by the maturity and breadth of CDC analysis and verification tools available. As CDCs are more understood, a new breed of domain crossings introduce challenging issues in the design of ASICs. These are Reset Domain Crossings (RDC), brought on by the rise of increased use of third party IPs, aggressive power management and the increased rise of the use of asynchronous resets. This webinar explores the differences between CDC and RDC analyses, and brings to light the importance of this separate analysis for accelerating design-to-market.

 

What You Will Learn

  • What RDC covers that CDC does not
  • How Questa RDC identifies and eliminates RDC errors
  • The appropriate time in the development cycle to deploy RDC

 

Who Should Attend

  • ASIC/IC and FPGA Design and Verification Engineers, Project Leads, and Managers

 

Details

 

What

Web Seminar: Gain a Design-to-revenue Edge in FPGA and SoC Designs with a Full Deployment of Clock-Domain Crossing Analyses and Verification

 

When

Wednesday the 10th of July 2019

 

Where

Online

 

Register

5:00 PM EST

 

26th of September FPGA Verification Day 2019
26th of September The Evertiq Expo Lund