This webinar will show the powerful combination of Xpedition Layout routing and HyperLynx SI DDRx Wizard batch simulation to produce optimal DDR4 memory routing in your design.
The basic steps will include routing the DDR circuit and simulating the layout in HyperLynx SI. The process includes providing details to Electrical Engineer and ECAD Designer so DDR will be “Correct by Construction” on the very first fabrication. Simulation allows you to find things that could be problems in a complicated layout. Learn how to set up rules so you have a proper set of routing constraints in Xpedition Layout for the DDR Circuit that will work 100% of the time in HyperLynx SI.
Learn Design Methodologies in the Constraint Manager that will save valuable time and can help speed up your design process.
What you will learn
Who Should Attend
What
Customer Webinar: DDR to HyperLynx
Where
Online
When
Wednesday the 15th of January 2020
Time
6:00 PM - 7:00 PM CEST
EDA
Electrical & Wire Harness Design
Electronic System level Design
Support
ALM
PLM
Education & Consulting
Vendors
InnoFour
Twentepoort Oost 61-02
7609 RG Almelo
The Netherlands
tel +31 546 454 530
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