Managing Electronics Systems Design Risk With An Optimized Verification Strategy

Managing Electronics Systems Design Risk With An Optimized Verification Strategy

Overview
Most organizations leave detailed design validation for lab prototype testing, but this approach discovers problems late in the design cycle, leading to board re-spins that introduce delays and raise project costs. Increasing PCB systems performance requirements coupled with a pressure to improve product quality are driving engineering teams to consider alternatives to their current validation approach.

 

Some organizations validate designs through detailed simulations right before fab out, but this a requires domain specialists who are spread thin within organizations. Best-practice design processes embrace digitalization, creating a digital twin that is validated early and often to minimize re-spins and actually shorten the overall design cycle. This session will cover research on best-practice process strategies to achieve zero-spin results, as well as the inherent risks if these processes are avoided. Later sessions in the series will address specific engineering technologies that could be deployed within any ECAD design flow.

 

Who Should Attend

  • Managers of PCB design teams

 

Details

What

Event: Managing Electronics Systems Design Risk With An Optimized Verification Strategy

 

When

Tuesday 21st of April

 

Where

Online

 

Time

3:00 PM - 4:00 PM CEST