An introduction to efficient VHDL verification using the open source UVVM

An introduction to efficient VHDL verification – using the open source UVVM presented by Espen Tallaksen

Overview

The UVVM usage is exploding and is supported and recommended by more and more FPGA and ASIC industry players. The reason for this is the significant improvement in verification efficiency and design quality achieved by using this methodology and library. UVVM yields a unique reusability, and great overview, readability, maintainability and extensibility – at no cost – only by promoting a very structured architecture at all levels. A European Space Agency project to extend the UVVM functionality has just finished, and a new project is started. On top of this, UVVM also provides open source interface models for AXI4-stream, AXI4-lite, Avalon MM, Avalon stream, SBI, SPI, I2C, GPIO, UART, GMII, RGMII and Ethernet, and a lot of other very useful verification functionality.

 

This presentation will show you the basics of making good testbenches, give you a fast introduction to UVVM Utility Library, and show you step-by-step how to get started in only 4 minutes. Entry level UVVM is really dead simple, and this will show you how and why.

 

What You Will Learn

  • Verification basics
  • Essentials of making a good testbench
  • What is UVVM
  • How to use the UVVM Utility Library
  • What are BFMs and how to use them
  • Testing data communication
  • Use of typical testbench procedures
  • UVVM and Testbench summary

 

Who Should Attend

  • Verification engineers and managers
  • FPGA Design and Verification Engineers

 

Details

What

Live Webinar: An introduction to efficient VHDL verification – using the open source UVVM presented by Espen Tallaksen

 

When

Wednesday the 13th of May, 2020

 

Where

Online

 

Time

14:00 - 15:00 CEST