Overview
Today’s leading-edge systems require a modern FPGA I/O optimization interface that enables you to quickly perform pin swapping and layout-based I/O optimization within the PCB design flow. Fact is, the lack of, or poor FPGA I/O optimization often leads to longer routing cycles and longer trace lengths which in turn result in the need for additional signal layers and vias which can impact signal integrity. A design tool flow with FPGA I/O Optimizer technology eliminates the barriers between FPGA and PCB designers and provides ‘correct-by-construction’ FPGA I/O assignment allowing pin swapping and layout-based I/O optimization within the PCB process.
The ability to read in, export and synchronize FPGA designers’ HDL and constraint files ensures full consistency during the iterative concurrent design process. Incidentally, it also allows creating high pin count FPGA PCB parts ready for instantiation in minutes. Modern FPGA I/O optimization helps you not only accelerate design time-to-market, but also reduces manufacturing costs.
What You Will Learn
Who Should Attend
Products Covered
What
Live Webinar: How Integrated FPGA-PCB I/O Co-Design Accelerates PCB Design and Reduces Costs
When
Tuesday the 21st of July, 2020
Where
Online
Time
3:00 PM - 4:00 PM CEST
EDA
Electrical & Wire Harness Design
Electronic System level Design
Support
ALM
PLM
Education & Consulting
Vendors
InnoFour
Twentepoort Oost 61-02
7609 RG Almelo
The Netherlands
tel +31 546 454 530
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