I Didnít Know Visualizer Could Do That

I Didn’t Know Visualizer Could Do That

Live Webinar

 

Overview:

Visualizer Debug Environment automates debugging for the digital design and verification of today's complex SoCs and FPGAs. Find bugs faster in the Visualizer Debug Environment, a high-performance, high-capacity debugger. Tightly integrated with both Questa Simulation and Veloce Emulation, it provides a full set of synchronized views that analyze waveforms, source code, connectivity and more for Verilog, SystemVerilog, VHDL, SystemC and C/C++.

 

In addition to being very intuitive and easy to use in either interactive debug or post simulation mode, Visualizer has several powerful features that improve debug productivity for SystemVerilog/UVM, transaction-level, RTL, gate-level and low-power design and verification.

 

What You Will Learn:

  • Visualizer effect on design debug without compromising simulation performance or visibility
  • Finding root cause faster using automated temporal causality trace back (Time cone view), biometric search
  • Debug at a higher level using Transaction viewer, FSM view, logic cone and schematic view
  • Tackle complex UVM testbench challenges in Post (Class in waveform, schematic view …) and Live Sim mode (breakpoints …)
  • Best in class lower power/UPF and RNM debug

 

Who Should Attend:

  • Design & Verification Engineers & Managers who are interested in debug

 

 

Details

What

Live webinar: I Didn’t Know Visualizer Could Do That

 

When

Tuesday the 30th of March 2021

 

Where

Online

 

Time

4:00 PM CEST