This webinar will address how multiprocessor simulation accelerates performance. The results show that when all CPU cores perform equally and the tasks are equally balanced and heavy enough, simulation performance gain will be proportional to the number of used CPUs.
The push for multiprocessor simulation drives the wish for better performance. While software providers talk about “time to bug” or “time to full coverage”, engineers are interested in cycles per second. They see “oceans” of available CPU cores and the inherent parallel structure of HDL verification tasks as compelling reasons to ask for multiprocessor simulation options.
The basic ModelSim and Questa were used in this presentation to run basic Verilog test benches. The examples run on a multicore CPU and demand no “exotic” undocumented beta switches or licenses.
What You Will Learn:
Who Should View:
What
Live Webinar: Linear Acceleration of HDL Simulation Using Naive Parallel Processing
When
Tuesday the 20th of April 2021
Where
Online
Time
2:00 PM CEST
EDA
Electrical & Wire Harness Design
Electronic System level Design
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