Open Verification Methodology

The Open Verification Methodology (OVM) is the first truly open, interoperable, and proven verification methodology based on the SystemVerilog IEEE 1800 language and delivers an open and unified class library and methodology for interoperable verification IP (VIP).

OVM supports design and verification engineers developing advanced verification environments that offer higher levels of integration and portability of VIP. The methodology is non-vendor specific and represents interoperability with multiple languages and simulators. OVM is fully open and includes a robust class library and source code.

OVM is fully supported by Questa, Mentor’s comprehensive, mixed-HDL verification platform and Veloce, Mentor’s advanced hardware-assisted verification and emulation solution, and delivers the most robust execution platform for OVM-based testbenches in the industry.

For detailed information on the OVM, or download the OVM Kit visit OVMWORLD.ORG


Multiple Levels of Abstraction
True system-level-to-RTL verification methodology.

Advanced Verification
Supports advanced verification technologies, such as constrained-random stimulus, functional coverage, and assertions.

Testbench Reuse
Includes a set of executable examples, libraries, and extensive documentation (the Advanced Verification Methodology Cookbook for SystemVerilog and SystemC) for developing modular, reusable testbenches.

Open Source
Open and non-proprietary code is freely available to anyone under an open-source Apache 2.0 license

Standard Languages
Based on standard languages, it uses only 100 percent LRM-compliant SystemVerilog and SystemC code. As a result, code is reusable and “future-proof.”

TLM Standard
Based on the OSCI TLM standard, implemented in both SystemC and SystemVerilog, making it easy to link to embedded software and transaction-level models.




The OVM is backward compatible with the Advanced Verification Methodology (AVM). The AVM, developed by Mentor Graphics®, was the industry’s first open-source verification methodology and served as the catalyst and the foundation for the joint development of the OVM. The AVM and the Verification Cookbook continue to serve many users as their verification methodology of choice, and Mentor will maintain support for the AVM under Apache 2.0 open-source terms. The OVM was specifically designed to be backward-compatible with the AVM, so testbenches and VIP created with the AVM can be easily ported to the OVM if desired.

The AVM was the first, true, system-level-to-RTL verification methodology that allows you to apply leading-edge verification technologies to designs at multiple levels of abstraction, using multiple languages. The AVM provides libraries of base classes and modules in open-source form and uses TLM interfaces as the communication mechanism between verification components. The AVM CookBook for SystemVerilog and SystemC kit includes extensive runnable examples and extensive, book-form documentation that discusses the different concepts introduced in each example.



For users with legacy verification IP written using the VMM, a version of VMM is now available for Questa under the Apache 2.0 open-source license. Questa’s powerful and comprehensive support for SystemVerilog-based design and verification flows made direct support of VMM for SystemVerilog possible after changes were made to the VMM to adhere to the IEEE 1800 standard. The resulting VMM source code for Questa is now more portable among SystemVerilog implementations than prior versions of VMM, making it easier for VMM users to transition to OVM over time.

The changes that were necessary to bring the VMM code into compliance with the IEEE 1800 SystemVerilog standard are distinguished with Mentor Graphics copyright notices in the source files in keeping with the Apache 2.0 open-source license agreement. While adoption of OVM has been rapid, migration of legacy VMM environments to OVM has been limited due to VMM source-code access and license restrictions. With access and license restrictions now lifted and with the general availability of VMM for Questa, users can now plan a smoother migration path to OVM that can include reuse of their legacy VMM IP and environments. To facilitate the use of VMM for Questa a companion whitepaper is also available for download with the open-source code.


OVM Solution Flow
Mentor offers a complete solution flow for the creation and verification of designs and testbenches following the OVM. System-level models written in TLM can be explored with Vista and then reused as the golden reference model within the OVM testbench created with Certe Testbench Studio. Questa MVC can be incorporated easily, leveraging the reusability power of OVM. inFact intelligent testbench stimulus generation will automatically generate testbench sequences using graph-based algorithms, creating meaningful, non-repeating stimulus. Simulation is achieved with the Questa advanced verification environment or via Veloce for hardware-assisted verification. Requirements are tracked, monitored, and analyzed with ReqTracer throughout the entire development and verification process, ensuring the project requirements are fully met and verified successfully.


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