PCB Design Perfection Starts in the CAD Library - Part 3

Part 3 - PCB Design Perfection Starts in the CAD Library

Chip Components Smaller Than 1608 (EIA 0603) - Tom Hausherr Mentor Graphics Corp.


The IPC-7351B standard when a chip component size is less than 1.6 mm X 0.8 mm there are 7 rule changes that every PCB designer or CAD librarian must be aware of –


  1. The Land (pad) snap grid changes from 0.1 mm to 0.02 mm
  2. The land size round-off changes from 0.05 mm to 0.01 mm
  3. The Toe goal changes from 0.35 mm to 0.2 mm
  4. The corner radius changes from 0.2 mm to 0.15 mm
  5. The courtyard excess changes from 0.25 mm to 0.15 mm.
  6. When entering the component min/max dimensions the “Nominal” Terminal dimensions are used for both the min & max fields
  7. The part placement grid changes from 0.5 mm to 0.1 mm


See Figure 1 for the dimensions of a standard 1005 (EIA 0402) component superimposed with its related land pattern. In this case, I decided to break 2 rules –


  1. Land size round-off 0.05 mm
  2. Land snap grid round-off 1.0 mm
  3. Tighten the tolerance on the component width (W = 0.5 mm) to +/-0.05


The land center to land center spacing is 1.0 mm which is perfect for 1.0 mm space via fanout and the placement courtyard width is 1.0 mm which is perfect for placing parts 1.0 mm from center to center.


When placing the 1005 (EIA 0402) in the PCB layout use a 0.1mm grid to optimize the part placement and via fanout.



Figure 1


The 1005 (EIA 0402) was made for 1mm pitch BGA fanout. In Figure 2 you can see 2 different fanout options and one is superior to the other. The fanout coming out the top has all the key features. The vias are 0.25 mm closer to the capacitor component terminals than the typical right/left fanout which decreases impedance and increases capacitance. Also, the top fanout vias snap to a 1 mm grid because the 1005 land pattern was snapped to a 0.1 mm grid system. The 0.5 mm via land (pad) diameter with 0.25 mm hole size and 0.7 mm plane anti-pad is perfect for 0.1mm trace/space technology. The trace width for the power fanout is 0.3 mm.



   Figure 2 


See Figure 3 for the dimensions of a standard 0603 (EIA 0201) component superimposed with its related land pattern. In this case, I decided to break 2 rules –

  1. Land size round-off 0.05 mm
  2. Land snap grid round-off 1.0 mm
  3. Use the “Least” environment due to component miniaturization


For chip components smaller than 1 mm X 0.5 mm I use the IPC-7351B Least Environment to prevent tomb-stoning. When 2 pin micro-miniature parts have too much solder volume tomb-stoning can occur in the reflow oven. The land size for the 0603 (EIA 0201) should be a minimum of 2 times the terminal lead size.


The land maximum value is still being tested by assembly shops, as tomb-stoning is the number 1 problematic issue with the 0603 (EIA 0201) chip component.



  Figure 3


Note: The placement courtyard width is 0.6 mm to compensate for the component width tolerance of +/-.03 mm.


One of the techniques that can be used to prevent tomb-stoning for the 0603 (EIA 0201) is to thin the paste stencil from 0.15 mm to a smaller value for every occurrence of this component in the paste mask stencil. See Figure 4. The responsibility of the stencil thickness thinning process is placed on the assembly shop and the stencil manufacturer (not the PCB designer). Assembly shops use various solder alloys that require unique stencil creation.



  Figure 5


See Figure 5 for the dimensions of a standard 0603 (EIA 0201) component superimposed with its related land pattern. If you normally use the “Most” environment, my recommendation for the 0603 (EIA 0201) land pattern is to use the “Nominal” environment. The IPC nominal land size for the 0603 is about 3 times the size of the terminal lead. For this 0603 micro-miniature component, stay away from the “Most” environment as the solder volume is more than 4 times greater than the terminal lead footprint.



  Figure 6


The 1005 (EIA 0402) & 0603 (EIA 0201) chip components are very compatible with 1 mm pitch BGA. In Figure 6 there are 2 uses for the 1005 and one in-between the vias and one via-in-pad method. Because the 1005 land centers are on 1 mm pitch, the capacitor land (pad) falls directly centered on the via. Via-in-Pad technology will increase PCB cost because these vias need to be plated, filled and surface finish on the capacitor pad. The 0603 fall in-between the vias for the 0.1 mm trace/space technology DRC. This solution will not increase PCB fabrication cost. The dot grid display is 0.05 mm.



  Figure 7


IPC does not have a “standard” on drafting items such as silkscreen and assembly outlines and polarity markings yet. There are several types of silkscreen outlines and polarity markings that are used for Non-polarized Chip parts, Polarized Capacitors, Diodes and LED’s.


For a standard Non-polarized chip there are 2 options. See Figure 7 for both options. One is a line that separates the 2 lands. The default size is 0.2 mm and the default silkscreen the land gap is 0.25 mm. The CAD librarian can change both the line width and the gap to achieve placing a line between two lands that only have a 0.3 mm Gap by simply changing the line width and gap rules to 0.1 mm.


   Figure 8


See Figure 8 for the silkscreen outline for the Chip Diode. The Chip Diode also has a Post Assembly Inspection Dot so you can visually verify if the assembly inserted the Diode or LED in the correct rotation. The Polarized Chip Capacitor would have the same exact silkscreen outline but without the 0.6 mm bar.


  Figure 9


The Assembly Drawing Outlines and Polarity Markings are totally different than the Silkscreen Outlines and Polarity Markings. The first most obvious difference is that the outline shape is 1:1 scale of the component body. This outline can be either the “Nominal” or “Maximum” component body size. Another difference is the Reference Designator is centered inside the component outline and is never moved or relocated. The reference designator default size is 1.5 mm height with a 10% line width.


The Reference Designator and Assembly Outline only change rules for micro-miniature parts. The Assembly Outline will grow as large as the placement courtyard in order to fit the Reference Designator inside the Assembly Outline. When the component gets smaller, the Reference Designator will decrease from the default 1.5 mm height to a sliding scale of values until it fits inside the assembly outline. The reference designator scaling width is always 10% of the height. The various reference designator heights for micro-miniature components are –

  • 1.5 mm
  • 1.25 mm
  • 1 mm
  • 0.75 mm
  • 0.5 mm (this is the smallest human readable text height)


See Figure 9 for the non-polarized and polarized capacitor, diode and resistor assembly outlines and Reference designators. Notice the absence of land pads. From all Chip and Molded Body components, the Land is removed from the SMT padstack to insure that the reference designators are unobstructed. Also, for CAD tools that have this feature, Right Reading Orthogonal is always recommended so when the component is rotated, the reference designator is always flipped to right reading orientation.



Figure 9


Coming Up

Additional brief topical articles will appear in future newsletters. You can also read more detail in my blog, which can be found at: http://blogs.mentor.com/tom-hausherr/


Written by Tom Hausherr CID+

EDA Library Product Manager

Mentor Graphics Corporation