Verilog Fundamentals for SystemVerilog


This course is not yet planned.

Verilog Fundamentals for SystemVerilog


Duration: 1 Day
Course Part Number: 226904

This class is a prerequisite for engineers who wish to take the SystemVerilog for Verification with Questa course but do not have a Verilog background. It will provide a basic understanding of Verilog so the student can utilize SystemVerilog for design verification.


Special emphasis is placed on the event queue, blocking and non-blocking assignments and other language underpinnings that are maintained and extended in SystemVerilog.

You will learn how to

  • Write and understand basic Verilog code
  • Describe the basic workings of the Verilog scheduler with event queues, blocking and non-blocking assignments


Key Topics

  • Introduction to Verilog
  • Basic modeling structure
  • Lexical conventions
  • Modules
  • Port declarations
  • Module instances
  • Data types
  • Procedural blocks
  • Timing controls
  • Blocking vs. Non-blocking Proc. assignments
  • Operators
  • Programming statements
  • Sensitivity lists
  • Continuous assignments
  • User defined tasks
  • User defined functions
  • File I/O


Intended for

  • Verification engineers planning to use SystemVerilog for their Hardware Verification Language (HVL) who do not already know Verilog.


  • Familiarity with concepts of simulation
  • Familiarity with Windows or UNIX operating systems


Student workbook table of contents

For more information:

InnoFour BV
Twentepoort Oost 61-02
The Netherlands
tel +31 546 454 530
fax +31 546 453 006