PCB Design Perfection starts in CAD Library - Part 16

PCB Design Starts in the CAD Library

The 3-Tier PCB Library Concept


The 3-Tier PCB library concept was originally created by IEC (International Electromechanical Commission) in 1999 and introduced to IPC in 2000. The concept had to be created as a solution for high density packaging for hand held devices to ruggedized military applications and everything in-between. The IPC-7351 and the IEC 61188-5-1 SMT land pattern standards for were specifically created to introduce this new concept in 2005. Before 2005, the IPC-SM-782 was a 1-Tier land pattern standard developed in 1985 and released in March 1987. The pad size of the IPC-SM-782 land pattern, compared to the new IPC-7351, fell in-between the Most and the Nominal environments.


The IPC-7251 land pattern standard for through-hole components is currently being developed. It also has a 3-Tier environment concept that apply to the hole sizes and annular rings.


Three land pattern geometry variations are supplied for each of the device families; Maximum Land Protrusion (Density Level A), Nominal Land Protrusion (Density Level B) and Least Land Protrusion (Density Level C). Here are the definitions for the 3-Tier (or 3 Level) PCB library system for both through-hole and SMD technology.


Density Level A : Maximum Land/Lead to Hole Relationship – The ‘maximum’ land pattern conditions have been developed to accommodate the most robust producability of the solder application method. The “Level A” land patterns are usually associated with low component density product applications. “Level A” land patterns accommodate wave or flow solder of leadless chip devices and leaded gull wing devices. The geometry furnished for these devices, as well as inward and “J”-formed lead contact device families, may provide a wider process window for reflow solder processes as well. “Level A” is used for ruggedized military applications and medical devices.


Density Level B : Nominal Land/Lead to Hole Relationship – Products with a moderate level of component density may consider adapting the ‘median’ land pattern geometry. The median land patterns furnished for all device families will provide a robust solder attachment condition for most soldering processes and should provide a condition suitable for wave, dip, drag or reflow soldering. “Level B” is primarily used for desktop applications, controlled environment devices and many consumer electronic products.


Density Level C : Least Land/Lead to Hole Relationship – High component density typical of portable and hand-held product applications may consider the ‘minimum’ land pattern geometry variation. Selection of the minimum land pattern geometry may not be suitable for all product use categories.


The use of classes of performance 1, 2, and 3 is combined with that of component density levels A, B, and C in explaining the condition of an electronic assembly. As an example, combining the description as Levels 1A or 3B or 2C, would indicate the different combinations of performance and component density to aid in understanding the environment and the manufacturing requirements of a particular assembly.


See Figure 1 for an example of the 3 different land pattern levels for chip components.


Figure 1


Let’s take a look at the IPC-7351B tables for the Chip Component family. Table 1 applies to all chip components equal to or larger than a 1608 (EIA 0603). The chip component family is referred to as “Rectangular or Square-End components for resistors, capacitors and inductors.


Table 1


Notice in Table 1 that the Side Goal value for the Least Environment is -0.05 mm. This does not mean that the land will be smaller than the component lead. There are several other factors that go into the land size calculation like Fabrication and Assembly tolerances and Component Lead tolerance. So whenever you see a negative value in a solder joint goal table, it is only adjusting the land size to neutralize the fabrication tolerance.


Table 2 is for “Rectangular or Square-End components for resistors, capacitors and inductors smaller than a 1608 (EIA 0603). Notice that the “Toe” goal and placement courtyard excess are affected the most. Also, the round-off factor is in 0.02 mm increments.


Table 2


See Figure 2 for an example of the 3 different land pattern levels for small outline package (SOP) components.


Figure 2


Let’s take a look at the IPC-7351B tables for the Gull Wing and Flat Ribbon L lead Component family. This component family includes Small Outline Diodes (SOD), Small Outline Packages (SOP) Small Outline Transistors (SOT) and Quad Flat Packages (QFP). Table 3 applies to all gull wing components with a pin pitch greater than 0.625 mm.


Table 3


Table 4 is for Gull Wing and Flat Ribbon L lead Component family with a pin pitch less than 0.625 mm.


Table 4


Notice in Table 4 that the only difference is in the “Side” solder joint goal. Also, Table 4 only represents the Small Outline Package (SOP) and the Quad Flat Package (QFP) component families.


There is a different IPC-7351B table for every component family lead type. The only component family group that only has one tier for the land size is the “Grid Array” components. Ball Grid Array (BGA), Land Grid Array (LGA), Column Grid Array (CGA and Pillar Column Grid Array (PCGA). This component family group has various placement courtyard excess sizes that are dependent on the lead size for the sole purpose of rework equipment access.


The “Bottom Only” leaded component families do not have a Toe, Heel or Side solder joint goal. Their solder joint goal is referred to as a “Periphery” and the land area is the same value on all sides. This includes “D-Shaped” leads for Pull-back lead QFN, Square and Rectangular leads for LGA’s and Round leads for BGA, CGA and LGA.


The SMT Land Pattern Naming convention has an M, N or L at the end of the name and the PTH Land Pattern Naming convention has an A, B or C at the end of the name to identify the Density Level with the exception of the Grid Array component families. There is also a "Proportional" environment for PTH libraries that uses a combination of IPC Level A, B and C depending on the hole size. Small holes use Level C, medium hole sizes use Level B and larger hole sizes use Level C or greater annular ring.


Coming Up

Additional brief topical articles will appear in future newsletters. You can also read more detail in my blog, which can be found at:http://blogs.mentor.com/tom-hausherr/


Written by Tom Hausherr CID+

EDA Library Product Manager

Mentor Graphics Corporation

Reprinted by permission from iConnect007