Live Webcast: Manage and Track Requirements in Your FPGA/ASIC Design Flow

Live Webcast: Manage and Track Requirements in Your FPGA/ASIC Design Flow

Due to the increased complexity associated with the delivery of electronics and the increased use of distributed design teams, there exists a growing need to formalize and streamline requirements tracking. In complex electronic systems, requirements need to be traceable from enterprise level requirements databases through system design artifacts and down into the individual subsystem detailed design source files and verification results.

 

This free webinar will cover the basic concepts of requirements tracing, the benefits of a requirements-driven design process, and how such an approach will assist you in meeting quality and standard compliance objectives, such as DO-254. Mentor Graphics ReqTracer is the powerful and flexible tool that will be presented and demonstrated in this webinar, enabling you to trace your system-level requirements all the way though your design implementation data and verification results.

 

What You Will Learn:

  • Design requirements tracing and analysis capabilities from source to the design implementation and verification results
  • Interfacing to key Mentor design tools such and Questa, HDL Designer and Certe Testbench Studio
  • Links design and verification data into requirements-aware relationships and confirms these requirements have been implemented and fully tested
  • Linking capabilities from diverse data in a variety of formats and bridging the traditional gap between requirements tools, design tools and test tools


Who Should Attend:

  • Project Managers
  • Design Engineers / Project Managers
  • Verification Engineers
  • FPGA Designers
  • VP Engineering/Operations


Details:

  • What: Manage and Track Requirements in Your FPGA/ASIC Design Flow
  • When: Thursday 11th of April 2013
  • Where: Online
  • Time: 16:00 PM CET
  • Duration: 1 hour
  • Registration: Web