Digital IC Design (Place & Route)

Digital IC Design

Innovative Technologies for Fast & High-Quality Design Closure at Advanced Process Nodes


Mentor Graphics IC implementation solutions, Olympus-SoC™ and Calibre® InRoute, deliver innovative technologies to solve the power, performance, capacity, time-to-market, and variability challenges encountered at the leading-edge process nodes.


The Olympus-SoC netlist-to-GDSII system performs variation- and power-aware rapid feasibility, including placement, advanced clock tree synthesis, and optimization for all mode/corner scenarios concurrently. Watch video ►


The Calibre InRoute design and verification platform includes all Olympus-SoC capabilities, plus true Calibre DRC and DFM signoff within the place and route environment.  Watch video ►

Benefits of Olympus tools:

  • Boost IC performance with advanced multi-corner, multi-mode (MCMM) optimization

  • Reduce power consumption in clock trees with MCMM clock tree synthesis

  • Improve yield with DFM-aware routing to address lithography issues in a timing context during implementation

  • Speed time-to-market with fewer design iterations, scalable multi-threading, and sign-off quality closure

  • Load and process designs of 100M gates or more with the industry's highest-capacity data structure

  • Reduce costs through high yields and fast time-to-market   Boost IC performance with advanced multi-corner, multi-mode (MCMM) optimization

Digital IC Design Products


Olympus-SoC is a complete IC design-for-variability implementation solution targeted at 65nm/45nm designs. Learn More ►


Calibre InRoute

Calibre InRoute enables designers to achieve signoff-quality manufacturing closure during physical design within the Olympus-SoC place and route system. Learn More ►


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