Comprehensive Memory Modeling - DDR Questa® Verification IP
Covered all the possible memory configuration scenarios? Finding it difficult to debug simulation for such a complex protocol? Ever wondered how to measure controller’s performance?
Mentor DDR Questa® Verification IP (DDR QVIP) solution provides a comprehensive memory modeling solution for exhaustive verification of memory controllers. It comes with a vast range of configuration options that allow specific device parts or custom parts to be modeled with ease. These memory models are qualified to run on all major simulators and can be used in both Verilog and System Verilog-UVM based environments.
They are equipped with the following advanced features:
- Efficient On-the-fly configurations using JSON files
- Easy to use memory APIs
- Powerful debug: Tracker Files, Transaction Visualization
- Extensive library of protocol assertion checks
- Built-in, unencrypted and extendable coverage model
What You Will Learn
- Memory evolution, application areas and current market trends
- Memory verification challenges
- DDR Questa® Verification IP’s unique features
- Technical demonstration
- DDR QVIP at leading edge chip makers
Who Should Attend
- IP, FPGA and SOC Design & Verification Engineers
- Engineering Managers
- Program Managers
Live webinar: Comprehensive Memory Modeling - DDR Questa® Verification IP
Tuesday 15th of September 2020
7:30 PM - 8:30 PM CEST
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