DDR4 Power-Aware Simulations in VX.2.6
Interactions between high-speed signals and a system’s power delivery network are both undesirable and unavoidable. These interactions will always degrade the design’s operating margin—the key question is, by how much?
Most signal integrity (SI) simulators use an idealized PDN model that neglects signal/PDN interactions and their impact on system margins. This is a particular challenge for DDR memory interfaces with many single-ended signals in the data and address buses. These drivers create switching noise that can adversely affect system reliability for improperly designed PDNs.
This webinar outlines the DDR4 power-aware analysis in HyperLynx VX.2.6 and how it makes power-aware analysis accessible, allowing designers to reduce their design risk. The design database and instructions for the analysis performed during this webinar are available for download from Support Center.
What you will learn:
- Definition of power-aware simulation
- Models needed to perform power-aware simulation
- Setting up HyperLynx SI/PI options, model library paths, and design settings
- How to use the new PDN and Channel Extractor
- How to extract a data byte lane on both signal and power pins
- How to simulate and compare ideal and non-ideal PDN results
Who Should Attend
- Engineering managers
- PCB Design engineers
- Signal Integrity Engineers
- Power Integrity Engineers
- PCB Layout designers
Customer Webinar: DDR4 Power-Aware Simulations in VX.2.6
Thursday the 19th of December 2019
06:00 PM - 07:00 PM