Portable Stimulus from IP to SoC – Achieve More Verification
Overview
With so much of the buzz about the emerging Accellera Portable Stimulus Standard centered around applications in the system level space, it might seem that this is the sole application for the technology. However, users have long been applying portable stimulus techniques across block, subsystem, and SoC-level environments to improve their verification productivity.
This presentation will show how Mentor’s inFact portable stimulus tool is applied across the verification spectrum and the spectrum of verification engines to achieve more verification with the same resources.
What You Will Learn
- How portable stimulus enables productive verification at block, subsystem, and SoC level
- How inFact enables reuse of SystemVerilog constraints with portable stimulus
- How inFact achieves coverage 10-100x faster than constrained random stimulus
- How inFact integrates into block, and SoC level environments
Who Should Attend
- Design and Verification Engineers and Managers
Products Covered
- Questa® inFact
Details
What
UVM 1800.2 & The New and Improved UVM Cookbook
When
Tuesday the 25th of September 2018
Where
Online
Register
This session will start with an overview of the changes in UVM 1800.2 from UVM 1.2 and 1.1d so you can be prepared to embrace the new Standard. To accompany this release, we have updated the online UVM Cookbook both to take advantage of some of the new features in UVM and also to guide you in creating testbenches that can be reused in all available engines, including emulation.
The 2018 Wilson Research Group ASIC and FPGA Functional Verification StudyIn this presentation, Harry Foster highlights the key findings from the 2018 Wilson Research Group Functional Verification Study, and provides his interpretation and analysis behind today's emerging trends.