UVVM – Advanced VHDL Verification – Made simple presented by Espen Tallaksen
Overview
The UVVM usage is exploding and is supported and recommended by more and more FPGA and ASIC industry players. The reason for this is the significant improvement in verification efficiency and design quality achieved by using this methodology and library. UVVM yields a unique reusability, and great overview, readability, maintainability and extensibility – at no cost – only by promoting a very structured architecture at all levels. A European Space Agency project to extend the UVVM functionality has just finished, and a new project is started. On top of this, UVVM also provides open source interface models for AXI4-stream, AXI4-lite, Avalon MM, Avalon stream, SBI, SPI, I2C, GPIO, UART, GMII, RGMII and Ethernet, and a lot of other very useful verification functionality.
Over the last couple of years, a lot of new functionality has been added via the ESA project. We have previously released the Scoreboard, and now lots of other new functionality has also been added. The most important of these are activity watchdog, Error injection, Monitor, Hierarchical VVCs and Specification Coverage.
This presentation will show how a good testbench architecture and a structured verification component approach will make advanced verification significantly easier to understand and control. VVCs and high- level transaction (SW-like commands) are explained, and of course we will go through the most important new features and functionality, - and explain how they will help you making a better testbench - and develop this much faster.
The UVVM testbench architecture with standardized VVCs and commands allow the best possible VHDL approach for verification efficiency, quality and reuse. Join the webinar and see how.
What You Will Learn
- Quality and Efficiency enablers
- Testbench architecture and harness
- Verification components functionality and architecture
- What are High level transactions and how to use them
- VVC standardization
- Scoreboarding and models
- Error injection and monitors
- Watchdogs
- Hierarchical VVCs
- Specification Coverage
Details
What
Live Webinar: UVVM – Advanced VHDL Verification – Made simple presented by Espen Tallaksen
When
Wednesday the 20th of May 2020
Where
Online
Time
14:00 - 15:00 CEST
This presentation will show you the basics of making good testbenches, give you a fast introduction to UVVM Utility Library, and show you step-by-step how to get started in only 4 minutes. Entry level UVVM is really dead simple, and this will show you how and why.
Net Classes and Clearances in PADS ProfessionalIn this customer-only webinar, we'll show you how to use Net Classes and Clearances that save valuable time and can help speed up your design process.