Analysis verification

Verification analysis and simulation are used to ensure that the finished design is ready for the next step of the design process. HyperLynx performs verification at both the schematic and PCB layout level:

• Schematic verification ensures the captured circuitry is functionally and electrically correct. There's no point in investing time and effort into modeling and simulation if the components are miswired, signals aren't properly terminated, or devices use incompatible voltage levels. Schematic verification allows these (and many other) issues to be identified and corrected up front in the design cycle.
• Post-layout PCB verification examines the board as it was actually laid out to ensure that design rules were followed properly, and that there are no unintended consequences associated with the final layout. Design rules are imperfect and are often impossible to follow exactly. HyperLynx uses a unique "progressive verification" methodology to perform analysis in stages, each more detailed and accurate than the last. This unique flow resolves as many potential design issues as possible, as quickly as possible, while requiring as little user analysis-specific expertise as possible.

Verification analysis doesn't have to wait until the schematic or board layout is complete - in fact, the earlier analysis is performed in the design process, the better. Sections of the design can be verified and implemented, so that issues can be identified and resolved. Finding problems early means that other sections of the design aren't affected, as is