Sophisticated FPGA Verification

ModelSim

ModelSim packs an unprecedented level of verification capabilities in a cost-effective HDL simulation solution.

ModelSim simulates behavioral, RTL, and gate-level code - delivering increased design quality and debug productivity with platform-independent compile. Single Kernel Simulator technology enables transparent mixing of VHDL and Verilog in one design.

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Advanced Code Coverage
Mixed HDL Simulation
Effective Debug Environment

Native compiled, single kernel simulator technology

ModelSim packs an unprecedented level of verification capabilities into a cost-effective HDL simulator and is ideally suited for the verification of small and medium-sized FPGA designs – especially designs with complex, mission-critical functionality.

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Advanced code coverage

Fast time to coverage closure

ModelSim’s advanced code coverage capabilities provide valuable metrics for systematic verification. Plus, ModelSim’s ease of use lowers the barriers for leveraging verification resources. All coverage information is stored in the highly efficient UCDB database. Coverage results can be viewed interactively, post-simulation, or after a merge of multiple simulation runs.
Mixed HDL simulation

Mixed language simulation

Comprehensive support of Verilog, SystemVerilog for Design, VHDL, and SystemC provide a solid foundation for single and multi-language design verification environments. An easy-to-use and unified environment provides FPGA designers the advanced capabilities they need for debugging and simulation.
Intuitive debug environment

Fast time-to-debug

ModelSim eases the process of finding design defects with an intelligently engineered debug environment that efficiently displays design data for analysis and debug of all hardware description languages. A broad set of intuitive capabilities for Verilog, VHDL and SystemC make it the ideal choice for ASIC and FPGA design.

Overview

In addition to supporting standard HDLs, ModelSim increases design quality and debug productivity. ModelSim’s award-winning Single Kernel Simulator (SKS) technology enables transparent mixing of VHDL and Verilog in one design. Its architecture allows platform-independent compile with the outstanding performance of native compiled code.

The graphical user interface is powerful, consistent, and intuitive. All windows update automatically following activity in any other window. For example, selecting a design region in the Structure window automatically updates the Source, Signals, Process, and Variables windows. You can edit, recompile, and re-simulate without leaving the ModelSim environment. All user interface operations can be scripted and simulations can run in batch or interactive modes. ModelSim simulates behavioral, RTL, and gate-level code, including VHDL VITAL and Verilog gate libraries, with timing provided by the Standard Delay Format (SDF).

MODELSIM OVERVIEW

Unified mixed language simulation engine for ease of use and performance
Native support of Verilog, SystemVerilog for design, VHDL, and SystemC for effective verification of sophisticated design environments
Fast time-to-debug, easy to use, multi-language debug environment
Advanced code coverage and analysis tools for fast time to coverage closure
Interactive and Post-Sim Debug available so same debug environment used for both
Powerful Waveform compare for easy analysis of differences and bugs
Unified Coverage Database with complete interactive and HTML reporting and processing for understanding and debugging coverage throughout your project
Coupled with HDL Designer and HDL Author for complete design creation, project management and visualization capabilities

2022 Wilson Research Group FPGA functional verification trends

This report presents those results from the 2022 Wilson Research Group Functional Verification Study that were focused on the Field-Programmable Gate Array (FPGA) segment. The findings from this study provide invaluable insight into the state of today’s FPGA market in terms of both design and verification trends.

Advanced Code Coverage

ModelSim’s advanced code coverage capabilities and ease of use lower the barriers for leveraging this valuable verification resource.

The ModelSim advanced code coverage capabilities provide valuable metrics for systematic verification. All coverage information is stored in the Unified Coverage DataBase (UCDB), which is used to collect and manage all coverage information in a highly efficient database. Coverage utilities that analyze code coverage data, such as merging and test ranking, are available. Coverage results can be viewed interactively, post-simulation, or after a merge of multiple simulation runs. Code coverage metrics can be reported by instance or by design unit, providing flexibility in managing coverage data.

The coverage types supported include:

Statement coverage
Number of statements executed during a run

Branch coverage
Expressions and case statements that affect the control flow of the HDL execution

Condition coverage
Breaks down the condition on a branch into elements that make the result true or false

Expression coverage
The same as condition coverage, but covers concurrent signal assignments instead of branch decisions

Focused expression coverage
Presents expression coverage data in a manner that accounts for each independent input to the expression in determining coverage results

Enhanced toggle coverage
In default mode, counts low-to-high and high-to-low transitions; in extended mode, counts transitions to and from X

Finite State Machine coverage
State and state transition coverage

Mixed HDL Simulation

ModelSim combines simulation performance and capacity with the code coverage and debugging capabilities required to simulate multiple blocks and systems and attain ASIC gate-level sign-off. Comprehensive support of Verilog, SystemVerilog for Design, VHDL, and SystemC provide a solid foundation for single and multi-language design verification environments. ModelSim’s easy to use and unified debug and simulation environment provide today’s FPGA designers both the advanced capabilities that they are growing to need and the environment that makes their work productive.

Effective Debug Environment

The ModelSim debug environment’s broad set of intuitive capabilities for Verilog, VHDL, and SystemC make it the choice for ASIC and FPGA design.

ModelSim eases the process of finding design defects with an intelligently engineered debug environment. The ModelSim debug environment efficiently displays design data for analysis and debug of all languages.

ModelSim allows many debug and analysis capabilities to be employed post-simulation on saved results, as well as during live simulation runs. For example, the coverage viewer analyzes and annotates source code with code coverage results, including FSM state and transition, statement, expression, branch, and toggle coverage.

Signal values can be annotated in the source window and viewed in the waveform viewer, easing debug navigation with hyperlinked navigation between objects and its declaration and between visited files.

Race conditions, delta, and event activity can be analyzed in the list and wave windows. User-defined enumeration values can be easily defined for quicker understanding of simulation results. For improved debug productivity, ModelSim also has graphical and textual dataflow capabilities.

ModelSim shares a common front end and user interfaces with Mentor's flagship simulator Questa. This allows customers to easily upgrade to Questa should they need higher performance and support for advanced Verification capabilities. Learn more about Questa

ModelSim

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