10X-100X Faster coverage closure
Questa intelligently generates stimulus to ensure that high test quantity does not come at the expense of high test quality. The result is a 10X-100X gain in verification productivity. Questa Verification Management reduces the time needed to manage regression testing and merge coverage results from hours to minutes. Questa also eases testbench programming by automatically generating coverage models.
The Questa Verification Solution is a comprehensive solution for verifying power management in low power designs. Questa Power Aware Simulation (PASim) verifies the power management architecture through both static analysis and simulation. Questa ADMS integrates with Questa PASim to verify power management in designs with analog/mixed-signal functionality. Questa CDC verifies clock-domain crossings inherent in designs with active power management. Questa Formal exhaustively verifies power control logic. And Questa Verification Management ensures that power management structures are thoroughly verified as part of coverage closure.
Powerful Unified Debug
Debug is one of the most important verification technologies and critical for achieving productivity in today's complex designs. The Questa Verification Solution combined with the new Questa Visualizer Debug for testbench and HW debug and Codelink for SW debug and HW/SW co-verification, provides maximum performance, capacity and automation for the complete cycle of SoC design and verification debug.
Questa Formal-Based Technologies offer the unique ability to root out obscure bugs and increase design confidence through exhaustive analysis. Questa offers a broad spectrum of formal solutions, ranging from fully automatic applications such as clock-domain crossing verification, code coverage closure and automatic formal checking to custom coded assertion property checking with high-powered formal engines. These solutions work as a complement to simulation-based methods and they boost verification productivity by targeting verification tasks that are otherwise difficult to complete.
Leading support for UVM
The Questa Verification Solution is the first verification platform with a UVM-aware debug solution that provides engineers essential information about the operation of their dynamic class-based testbenches in the familiar context of source code and waveform viewing.
Questa lets you see the component hierarchy, class definition tree, and other UVM settings specific to your testbench to make it easier to understand the operation of your verification environment. Together with UVM Framework, UVM Connect, and Mentor’s Verification IP, the Questa verification solutions provide an unmatched environment.
Functional Safety / ISO 26262
SGS-TUV Saar certified Software Tool Qualification Reports for Questa Simulation, Questa Verification Management and Questa Clock Domain Crossing (CDC) to provide any tool confidence level (TCL) and support for all assumed use cases. Questa Simulation provides comprehensive verification reducing the risk of validating complex automotive designs. Questa Verification Management provides necessary insight for coverage and metric driven flows required to satisfy ISO 26262. Questa CDC provides clock domain crossing analysis for verifying synchronization and metastability effects