Functional Verification

Questa® Clock-Domain Crossing (CDC) Verification

The industry’s most comprehensive and easy-to-use clock-domain crossing verification solution.

Immediate productivity
Ease of Use
Low Noise, High Accuracy
Low Power Intent Awareness

CDC

Metastabilty from the intermixing of multiple clock signals is not modeled by simulation. Unless you leverage exhaustive, automated Clock-Domain Crossing (CDC) analyses to identify and correct problem areas, you will inevitably suffer unpredictable behavior when the chip samples come back from the fab. Bottom-line: automated CDC verification solutions are mandatory for multi-clock designs.

When Good Clocks Go Bad

Designers increasingly use advanced multi-clocking architectures to meet the high-performance and low-power requirements of their chips. An RTL or gate-level simulation of a design that has multiple clock-domains does not accurately capture the timing related to the transfer of data between clock-domains. As a consequence, simulation does not accurately predict silicon behavior, and critical bugs may escape the verification process.

The Solution: Questa CDC Verification

Questa CDC Solutions identify errors that have to do with clock-domain crossings – signals (or groups of signals) that are generated in one clock-domain and consumed in another. It does so with structural analysis and recognition of clock-domains, synchronizers, and low power structures (via UPF); and with generation of metastability models for reconvergence verification. The technology checks all potential failure modes and presents to the user familiar schematic and waveform displays. Additionally, in concert with simulation this technology can be used to inject metastability into functional simulation to verify the DUT correctly processes asynchronous clocks.

Features

Statically verifies that all signals crossing asynchronous clock-domain boundaries are guarded by CDC synchronizers
Checks integrity of clock-domain crossing (CDC) paths in the design
Supports an extensive set of pre-defined and user-defined CDC schemes
Comprehensively verifies the structure, protocol and reconvergence of all schemes
Uses Questa CDC and UPF power intent files to verify that introduction of low-power circuitry does not introduce CDC issues
Integrated GUI debugging
Tight integration with Questa Formal
Integration / results reporting with IEEE standard UCBD to electronically communicate progress and success into the main verification database (via Verification Manager).

Benefits

Immediate productivity: Questa CDC automatically identifies your clock and clock distribution strategy, minimizing set up time. Simply read in your RTL design and Questa CDC will pinpoint all potential CDC issues – no testbench is required.
Ease of use: Questa CDC supports Synopsys Design Constraints (SDC) format constraints for clock and port domain settings and includes a TCL scripting environment with powerful control and reporting capabilities
Low Noise, High Accuracy: Fewest false negatives in the industry, so you don’t waste time chasing non-issues.
Familiar Visualization: CDC-centric analysis and debugging GUI leverages familiar schematics and waveforms where appropriate.
Low Power Intent Awareness: reuses your UPF file without modification to ensure low power circuitry does not introduce CDC-related issues.
SoC-level scalability: Questa CDC's high performance analysis can process 100-million-gate designs and its hierarchical capabilities enable unlimited capacity.
Focused integration with simulation: Patented, automated metastability injection is the only way to find complex CDC reconvergence bugs.
Verification management: Automatic coverage reporting for CDC protocol and reconvergence verification (via UCDB) enables you to measure CDC verification progress and the quality of the testbench with respect to CDC protocols, and effectively manage the overall verification process.

When are you done running cdc?

Poorly designed clock-domain crossings kill chips. They kill products. They slip through simulation, are elusive in hardware validation, and can masquerade as other issues. The designer is held accountable for the results, and if not careful can be left in the lab for long nights of frustrating debug - or worse. Like the age-old verification question "how do you know when you're done testing?" It's fair to ask the designer "how do you know when to stop looking for CDC issues?" But in this era of many clock and power domains, third party or legacy IP, and intense PPA pressure, rigorous design and reviews are simply not enough. So how much CDC checking is enough?

In this session you will learn whether or not you might still have an asynchronous clock or reset issues lurking in your design, despite having identified the crossings, ensured synchronizers are present, and reviewed your code – or even already run CDC analysis, ensuring that all CDCs are solid.

On-demand Web Seminar

Note

If the user is knowledgeable about formal verification and SVA syntax, and they want to use Questa Formal to more deeply investigate a given CDC issue, the seamless integration between Questa Formal and Questa CDC supports exactly this kind of detailed analysis. Finally, results reporting via the IEEE standard Unified Coverage Database (UCDB) allows Questa CDC users to electronically communicate their progress and success with CDC analysis into the main verification database (via Verification Manager).

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