Functional Verification

Questa® Power Aware Simulator

The Questa® Power Aware Simulator enables design teams to verify the architecture and behavior of active power management planned for the implementation, but starting much earlier in the design process.

Very active power management

Verification of active power management at the RTL stage makes it possible to explore alternative power management approaches long before implementation begins, to achieve the greatest power reduction at the least cost. Verification of active power management in the post-synthesis Gate-Level netlist stages makes it possible to ensure that synthesis and manual transformations have correctly preserved the active power management architecture and its behavior.

How Questa Power Aware Simulation Works

Given a description of power intent expressed in the industry-standard Unified Power Format (UPF), the Questa Power Aware Simulator

  • partitions the HDL design into power domains,
  • adds isolation, level-shifting, and retention cells, and
  • integrates the power supply network into the design to power each domain

 

The augmented HDL design can then be simulated with full control over the power state of each domain, for accurate modeling of the effects of active power management on the design’s functionality.

Automatic Detection of Power Management Errors

The Questa Power Aware Simulator automatically detects power management errors in both the architecture and the behavior of the power management system. Static checks during compilation of the UPF identify architectural issues such as missing isolation or level-shifting cells. Dynamic checks during simulation identify behavioral issues such as incorrect control sequencing for powering up or powering down portions of the design. All checks can be enabled or disabled independently to configure the appropriate set of checks for a given design.

Automatic power management error checks include checks such as the following:

  • Level shifters and Isolation cells present where needed
  • Retention registers saved before power off
  • Latch enable is correctly set when retention occurs
  • Clock is disabled during power down
  • Isolation is enabled during power down
  • Inputs do not toggle during power down
  • Retention/Isolation power is on and stable during power down
  • Primary power is on and stable during power up
  • Non-retention registers are reset at power up
  • Power control signals do not glitch
  • Dynamic voltage changes are correctly mediated by level shifters

Visualization and Ebugging of the Power Management Architecture

The effects of active power management on the design’s structure and behavior are reflected in the waveform view, the schematic view, and the power state/transition view. The waveform view highlights signals that have been corrupted due to powering down, as well as signals that have been isolated to avoid corruption. The schematic view color codes design elements to indicate the power domain to which they belong. The power state/transition view presents the current power states of the system and each of its power domains, and the most recent power state transition, in both an FSM-like form and a tabular form similar to a UPF power state table.

Power State/Transition Coverage Data Collection

Power states and transitions are recorded in Mentor’s Unified Coverage DataBase (UCDB) for integration with verification planning and management. This enables incorporation of power aware simulation goals into the verification plan so they can be tracked for coverage closure.

An Integrated Approach to Power Domain and Clock Domain Crossing Verification

Reducing power consumption is essential for both mobile and data center applications. The challenge is to lower power while minimally impacting performance. The solution has been to partition designs into multiple power domains which allow selectively reducing voltage levels or powering off partitions. Traditional low power verification validates only the functional correctness of power control logic, it does not validate the impact of power logic on multi-clock logic. This paper explains the new low power CDC issues and the CDC verification techniques developed to verify low power designs.

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