Key Features
- Assertion and property-based verification for HLS models
- Find difficult to detect bugs without writing complex testbenches
- Sequential equivalence comparison of HLS and RTL for Independent verification
- Replaces time consuming simulation regressions with fast results
- Automatic generation of RTL verification environment re-using users C/C++/SystemC testbench
- Compares functionality of users C/C++/SystemC behavior interactively with RTL