The SCVerify flow in Catapult automatically generates the verification infrastructure for verifying the functionality of the HLS generated RTL against the users original source code and re-uses the original C++/SystemC testbench. In addition to functional comparison, it includes translation of assertions and coverage from the HLS level to the RTL level for coverage closure. SCVerify supports Mentor QuestaSim/ModelSim, Synopsys VCS and Cadence IUS/NCSim simulation environments.
The UVMf flow in Catapult automatically generates a complete UVM environment using the UVM Framework (UVMf). The automatic generation includes re-use of the original C tests wrapped in SystemVerilog as a sequence generator, the source HLS C model as a UVM predictor, a scoreboard that will automatically compare the results from the HLS C model to the resulting RTL in simulation. The environment also automatically generates a small test set of SystemVerilog constrained-random UVM sequences into each of the user agents that the user could use as a starting point to easily add more tests. The UVMf flow supports Mentor QuestaSim.
SLEC HLS formally proves the equivalence of the Catapult HLS generated RTL to the designer’s original C/C++/SystemC code. It is based on patented sequential analysis technology which enables it to finds design errors that other tools miss because it can compare the functionality of a HLS system-level model with its corresponding synthesized RTL design across all possible input sequences.
