- Assertion and property-based verification for HLS models
- Find difficult to detect bugs without writing complex testbenches
- Sequential equivalence comparison of HLS and RTL for Independent verification
- Replaces time consuming simulation regressions with fast results
- Automatic generation of RTL verification environment re-using users C/C++/SystemC testbench
- Compares functionality of users C/C++/SystemC behavior interactively with RTL
The SCVerify flow in Catapult automatically generates the verification infrastructure for verifying the functionality of the HLS generated RTL against the users original source code and re-uses the original C++/SystemC testbench. In addition to functional comparison, it includes translation of assertions and coverage from the HLS level to the RTL level for coverage closure. SCVerify supports Mentor QuestaSim/ModelSim, Synopsys VCS and Cadence IUS/NCSim simulation environments.