High-Level Synthesis

HLS Verification

The SCVerify flow in Catapult automatically generates the verification infrastructure for verifying the functionality of the HLS generated RTL against the users original source code and re-uses the original C++/SystemC testbench. In addition to functional comparison, it includes translation of assertions and coverage from the HLS level to the RTL level for coverage closure. SCVerify supports Mentor QuestaSim/ModelSim, Synopsys VCS and Cadence IUS/NCSim simulation environments.

Assertion and property-based verification for HLS models
Automatic generation of RTL verification environment re-using users C/C++/SystemC testbench
Compares functionality of users C/C++/SystemC behavior interactively with RTL

High-Level Synthesis (HLS) Verification with the Catapult Platform has three categories:

Automatic/formal checking of users’ HLS targeted C++/SystemC code finding errors before synthesis.
Simulation based verification comparing functionality of users C++/SystemC source with generated RTL including metrics such as coverage and assertions.
Formal verification of equivalence of the users' C++/SystemC code with the generated RTL from synthesis Catapult® DesignChecks formally verifies the design to find bugs and issues in the user’s code before starting the HLS process. It identifies defective code using static checks for defined properties and comprehensively verifies assumptions through formal proofs of user-defined assertions.

The UVMf flow in Catapult automatically generates a complete UVM environment using the UVM Framework (UVMf). The automatic generation includes re-use of the original C tests wrapped in SystemVerilog as a sequence generator, the source HLS C model as a UVM predictor, a scoreboard that will automatically compare the results from the HLS C model to the resulting RTL in simulation. The environment also automatically generates a small test set of SystemVerilog constrained-random UVM sequences into each of the user agents that the user could use as a starting point to easily add more tests. The UVMf flow supports Mentor QuestaSim.

SLEC HLS formally proves the equivalence of the Catapult HLS generated RTL to the designer’s original C/C++/SystemC code. It is based on patented sequential analysis technology which enables it to finds design errors that other tools miss because it can compare the functionality of a HLS system-level model with its corresponding synthesized RTL design across all possible input sequences.

Key Features

Assertion and property-based verification for HLS models
Find difficult to detect bugs without writing complex testbenches
Sequential equivalence comparison of HLS and RTL for Independent verification
Replaces time consuming simulation regressions with fast results
Automatic generation of RTL verification environment re-using users C/C++/SystemC testbench
Compares functionality of users C/C++/SystemC behavior interactively with RTL

Smoke Testing a High-Level Synthesis Design

Designing hardware using C++ and C++ testbenches brings orders of magnitude speed-up to simulation. But after High-Level Synthesis (HLS), teams need a way to quickly ensure that the newly-generated RTL is functionally the same as the original untimed C++. They don’t want to create an RTL testbench in order to make this comparison. What teams need is an automated smoke test to quickly make the comparison with very little effort. This paper covers how SCVerify, part of the Catapult HLS Platform, provides teams with the ability to perform push-button smoke testing.

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