High-Level Synthesis

Low-Power HLS

Catapult Low-Power (LP) is the industry’s first High-Level Synthesis (HLS) tool that targets power as an optimization goal. It takes advantage of PowerPro®’s best-in-class power analysis and optimization technology by embedding it at the core of the HLS engine.

C/C++SystemC HLS with built-in power awareness
Measures and compares power across multiple architectures
Automatically synthesizes low-power RTL with fine grained optimizations

This provides a closed-loop optimization flow across power, performance and area from architecture definition to RTL implementation.

A designer uses Catapult LP to explore different hardware architecture and measures the power, performance and area of each solution. Catapult’s interactive analysis tools assist in design refinement. During the synthesis process, Catapult LP automatically performs fine grained power-saving optimizations aimed at minimizing switching activity in the RTL to deliver the greatest power savings.

Key Features

C/C++/SystemC HLS with built-in power awareness
Measures and compares power across multiple architectures
Automatically synthesizes low-power RTL with fine grained optimizations
Leverages PowerPro’s deep sequential analysis technology
Sequential clock gating for fine grained power reduction of register, clock tree, and logic power
Loop and memory optimization for architecture exploration and optimization

White Paper

Catapult LP for a Power Optimized ESL Hardware Realization Flow

This paper describes, in general, the Catapult® flow for exploring low-power architectures, and it discusses in detail the low-power optimization results achieved using the Catapult LP design flow. The case study was conducted using real customer designs. Designs were synthesized using Catapult with and without low-power optimizations turned on. With low-power optimizations on, Catapult uses Calypto's PowerPro® technology under the hood for implementing RTL power optimization techniques and for estimating a design’s power usage.

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