IC Design

Calbre DESIGNrev

For engineers integrating and assembling complete chips, the process of going from first pass integration to successful tape-out can be lengthy and difficult. With design size and complexity increasing, traditional layout editors lack the capability to quickly and efficiently visualize, revise and stream-out layout data.

Performing simple tasks on large full-chip GDSII and OASIS® files, and preparing the design for the mask manufacturing process (chip finishing), often can take hours, delaying tape-out.


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Calibre® DESIGNrev™

Speeds full-chip design completions and tape-outs by rapidly loading, displaying and saving large GDSII and OASIS® files.

Handle Large Design Files Quickly and Efficiently

Calibre DESIGNrev can handle the largest design files quickly and efficiently. Chip finishing can also be quickly performed in DESIGNrev, giving designers the capability to merge actual cell representations of abstracts, place logo cells, replace vision cells, create seal rings, perform metal fill and via insertion, add critical dimension (CD) patterns, add corner stress relief patterns, modify polygon, cells and more in post verification, compare original data to modified version, and verify trace net connections.

Identify and Fix Physical Verification Errors

In addition, Calibre DESIGNrev allows engineers to quickly zoom to regions of interest, identify and fix physical verification errors, and conveniently re-invoke Calibre DRC™ and Calibre LVS. Chip finishing prepares a design for the manufacturing process. Finishing is performed within the original design data and GDSII before being handed over for mask making. Within Calibre DESIGNrev, designers can merge data (actual cell representations of abstracts, placement of logo cells and revision cell replacement), create data (seal rings, metal fill, via insertion, post verification modifications), and verify and compare data (post layout verification, XORs, trace net connections) at the full chip level.

Features & Benefits

  • Enables realtime signoff DRC checks during design modification (requires Calibre RealTime license)
  • Dramatically reduces time to tape-out with robust revision and iteration loop capabilities
  • Allows convenient re-verification of the full design, or only the data that has been modified
  • Efficiently automates chip finishing tasks
  • Supports the open standard TCL/TK macro language for extensive tool customization.
  • Accesses data within the GDSII or OASIS® database

Resolving cell name conflicts for efficient layout hierarchy

Duplicate cell names across multiple IP in an SoC can result in unexpected layout results at the full-chip level, larger file sizes, and the inability to run layout verification tools efficiently in hierarchical mode. The Calibre DESIGNrev tool provides a simple, efficient, automated solution for identifying, renaming, and reporting these cell name conflicts. The outcome is a clear and consistent design process, straightforward chip assembly, a clean and meaningful design hierarchy, faster EDA tool runtimes, and faster time to tapeout.

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