Calibre DESIGNrev can handle the largest design files quickly and efficiently. Chip finishing can also be quickly performed in DESIGNrev, giving designers the capability to merge actual cell representations of abstracts, place logo cells, replace vision cells, create seal rings, perform metal fill and via insertion, add critical dimension (CD) patterns, add corner stress relief patterns, modify polygon, cells and more in post verification, compare original data to modified version, and verify trace net connections.
For engineers integrating and assembling complete chips, the process of going from first pass integration to successful tape-out can be lengthy and difficult. With design size and complexity increasing, traditional layout editors lack the capability to quickly and efficiently visualize, revise and stream-out layout data.
Performing simple tasks on large full-chip GDSII and OASIS® files, and preparing the design for the mask manufacturing process (chip finishing), often can take hours, delaying tape-out.