How can I benefit from a single verification flow?

A single verification flow allows the use of a single set of rule files for both cell/block and full-chip verification. It eliminates the discrepancies caused by out-of-synch verification flows. Discrepancies need to be reconciled and resolved individually, potentially extending the tape-out period and causing time-to-market delay. A single verification flow also eliminates the duplicate maintenance and training required when employing verification tools from multiple vendors.