Physical Verification with Calibre®

Calibre Pattern Matching

Calibre® Pattern Matching supplements multi-operational text-based design rule checks with an automated visual geometry capture and compare process. This visual approach is not only powerful in its ability to capture complex pattern relationships simply and quickly, but also easy to incorporate into mixed tool flows—enabling users to easily create new applications solving difficult problems. As part of the Calibre nmPlatform, Calibre Pattern Matching is used in conjunction with a wide range of other Calibre tools to solve complex layout issues with ease across design, manufacturing, and wafer test.

Features and Benefits

Easy to Use

  • Automated pattern capture via a GUI or batch scripting environment
  • Specify exact match or add controlled variability with pattern constraints
  • Use with multiple Calibre tools as part of a single SVRF deck
  • Run in all major design environments using existing Calibre integrations

Improved productivity

  • Supports fast, automated design enhancements that improve yield and design quality
  • Reduces debug time significantly
  • Enables faster rule deck development, even at the most advanced nodes, while ensuring precise compliance with the most complex engineering specifications

Broad range of applications

  • Complex DRC
  • Hotspot and defect geometry identification
  • Contextual waivers
  • IP alteration identification
  • Multi-layer patterns
  • Automated layout enhancements
  • Non-Manhattan validation
  • Complex/Analog device verification
  • Layout retargeting

Precise rule checks

  • Quickly and accurately implement complex design constraints and rule checks previously difficult or impossible to perform
  • Enables additional focused checking and analysis on matched patterns

Improved communication

  • Shared pattern libraries between design, verification, manufacturing and test ensure consistency and accuracy across flows and between teams.
  • Fast, accurate, and uniform updates for recently-identified patterns.

Calibre & 3rd Party Integration

  • Single rule deck integration with Mentor products
  • Integrated with Olympus-SoC™ and Calibre® InRoute™ tools to provide Calibre signoff-quality auto-fixing and verification during digital implementation
  • Can be used in Calibre nmPlatform integration with all major P&R and custom design environments for Calibre signoff-quality verification

Complex Verification Simplified

Calibre Pattern Matching enables the creation of physical verification or design methodology checks that were previously difficult or operationally impossible to create—enabling designers to deliver higher-performing products with reduced design variability, even at the most advanced nodes.

Calibre Pattern Matching significantly simplifies the verification of complex layouts while improving the accuracy and precision of design implementation and verification.

Calibre nmPlatform Integration

Calibre Pattern Matching can be used with multiple Calibre tools as part of a single SVRF deck—no stream-outs/stream-ins or complex scripts needed. Integration with Olympus SoC and Calibre InRoute tools enables pattern-matching-driven place and route with auto-fixing and verification that meet Calibre signoff quality standards. This direct integration enhances performance and reduces turnaround times for even the most complex and advanced designs.

Design Environment Integration

The Calibre nmPlatform’s integration with all major design creation environments means you can run Calibre Pattern Matching anywhere you run Calibre nmDRC. Design teams can invoke Calibre Pattern Matching functionality from 3rd party P&R and design tools. Results can be debugged in the same environment used to debug Calibre nmDRC results.

Automated Pattern Capture, Definition and Search

Designers can create patterns manually or use the automated pattern capture to create multiple patterns in a single step. Pattern libraries can be created for design methodologies, manufacturing processes, or other categorizations, as applicable.

Using Calibre Pattern Matching in physical verification and design implementation is as easy as 1-2-3.

Automated Design Enhancement

Foundries and fabless/fablite companies can more quickly, easily, and accurately identify opportunities for and apply design enhancements to improve yield and/or design quality and reliability.

Streamline Communication

Shared pattern libraries ensure accurate, quick updates with a level of simplicity not possible with traditional flows. Faster, more accurate communication using visual patterns (rather than text-based abstractions) makes the entire implementation and verification process faster and more efficient.

From expanding physical verification rule checking, to simplifying the task of avoiding known yield detractors, to enhancing workflows such as design rule waiver recognition, Calibre Pattern Matching is a valuable tool throughout the design, verification, and test process.

Learn More About Calibre Pattern Matching

What They're saying

"With DRC+ (Pattern Matching), we are improving upon the traditional approach ang giving customers increased visibility into potential manufacturability issues, earlier in the design flow."

Senior Vice President, design enablement Globalfoundries

What They're saying

"As TSMC customers move to 28nm and beyond, they want tools that allow them to work at higher levels of abstraction. and give them confidence that their designs can meet performance and low power goals and achieve yields that TSMC processes are capable of delivering."

S.T. Juang senior director of design infrastructure marketin, TSMC

What They're saying

"We use Calibre Pattern Matching to creat and apply a Calibre-based yield-detractor design kit that helps identify and eliminate design patterns that impact production ramp-up time."

Deepak Sabharwal, general manager, IP products & services eSilicon

What They're saying

"To help our customers create manufacturing-ready designs, we use Calibre Pattern Matching to create and use a yield detractor database to fix most of the litho hotspots in the block level. Then we perform fast signoff DFM litho checking at the chip level using an integrated solution with Calibre Pattern Matching and Calibre LFD. By offering a solution for manufacturability robustness that is built on the Calibre platform, we are seeing ready customer adoption of SMIC's DFM solution."

Minhua Ji, senior vice president SMIC